mass-rename of modules to soc.fu.*

diff --git a/src/soc/fu/alu/formal/proof_input_stage.py b/src/soc/fu/alu/formal/proof_input_stage.py
index 347ab7d42e6be01d7ad8dd0daf0e62b6d3865aa1..53e1dc361bf28c0886301ab766b3c5c1e4bbbfbf 100644 (file)
--- a/src/soc/fu/alu/formal/proof_input_stage.py
+++ b/src/soc/fu/alu/formal/proof_input_stage.py
@@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.alu.input_stage import ALUInputStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.input_stage import ALUInputStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/alu/formal/proof_main_stage.py b/src/soc/fu/alu/formal/proof_main_stage.py
index f102fc2b1726ed4d87b9a7415f09b9c7c9438423..601a487576e39d9da2682095818b6773ef544b42 100644 (file)
--- a/src/soc/fu/alu/formal/proof_main_stage.py
+++ b/src/soc/fu/alu/formal/proof_main_stage.py
@@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.alu.main_stage import ALUMainStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.main_stage import ALUMainStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/alu/formal/proof_output_stage.py b/src/soc/fu/alu/formal/proof_output_stage.py
index 288da07170b9c46bc52e38d1e728e10e835b47e3..9e33f14891550040f3f145863842e94f8ee2897b 100644 (file)
--- a/src/soc/fu/alu/formal/proof_output_stage.py
+++ b/src/soc/fu/alu/formal/proof_output_stage.py
@@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.alu.output_stage import ALUOutputStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.output_stage import ALUOutputStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/alu/input_stage.py b/src/soc/fu/alu/input_stage.py
index 75207324a931265d2e8e4596415e87083b331568..fd3fd1edd78c097acc7d242781e52ac317fac6dc 100644 (file)
--- a/src/soc/fu/alu/input_stage.py
+++ b/src/soc/fu/alu/input_stage.py
@@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
 from soc.decoder.power_enums import InternalOp
-from soc.alu.pipe_data import ALUInputData
+from soc.fu.alu.pipe_data import ALUInputData
 from soc.decoder.power_enums import CryIn
 
 

diff --git a/src/soc/fu/alu/main_stage.py b/src/soc/fu/alu/main_stage.py
index 51001663a5dcaaf55f2df8f2b2823e2f7f202c18..dd03b7865e8c938126daf849c2ef5d3d25f6307b 100644 (file)
--- a/src/soc/fu/alu/main_stage.py
+++ b/src/soc/fu/alu/main_stage.py
@@ -5,7 +5,7 @@
 # output stage
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
-from soc.alu.pipe_data import ALUInputData, ALUOutputData
+from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
 

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 1253795708f6f4e86c01378c0a1eca7a4cca441c..c93fec5be47e8d04ba646a57292ef789f17e1cb0 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -3,7 +3,7 @@
 # register
 from nmigen import (Module, Signal, Cat, Repl)
 from nmutil.pipemodbase import PipeModBase
-from soc.alu.pipe_data import ALUInputData, ALUOutputData
+from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
 

diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index c386397aa2f26b0b62550c260ef56aff529c24de..7c91349a0789675c6a4e40883c5147a729736849 100644 (file)
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -1,6 +1,6 @@
 from nmigen import Signal, Const
 from nmutil.dynamicpipe import SimpleHandshakeRedir
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from ieee754.fpcommon.getop import FPPipeContext
 
 

diff --git a/src/soc/fu/alu/pipeline.py b/src/soc/fu/alu/pipeline.py
index e8dd19911d0a3ab264df707aee61742bc41dc672..3a065b2e01b416182858b76a87a3f1e67118c103 100644 (file)
--- a/src/soc/fu/alu/pipeline.py
+++ b/src/soc/fu/alu/pipeline.py
@@ -1,8 +1,8 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
-from soc.alu.input_stage import ALUInputStage
-from soc.alu.main_stage import ALUMainStage
-from soc.alu.output_stage import ALUOutputStage
+from soc.fu.alu.input_stage import ALUInputStage
+from soc.fu.alu.main_stage import ALUMainStage
+from soc.fu.alu.output_stage import ALUOutputStage
 
 class ALUStages(PipeModBaseChain):
     def get_chain(self):

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index f42112e1805498a08b800aa50e8024dffdc5eb73..138ad3e1687b1e2450e49794b97d94016ffe131e 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -12,9 +12,9 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
-from soc.alu.pipeline import ALUBasePipe
-from soc.alu.alu_input_record import CompALUOpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.pipeline import ALUBasePipe
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.pipe_data import ALUPipeSpec
 import random
 
 class TestCase:

diff --git a/src/soc/fu/branch/formal/proof_input_stage.py b/src/soc/fu/branch/formal/proof_input_stage.py
index fb097c87d04a8e21e94e09c9d2d184fecdfbd3ef..3ac3ac891de5f80b933201c38420bd8ddfdd4596 100644 (file)
--- a/src/soc/fu/branch/formal/proof_input_stage.py
+++ b/src/soc/fu/branch/formal/proof_input_stage.py
@@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.alu.input_stage import ALUInputStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.branch.br_input_record import CompBROpSubset
+from soc.fu.alu.input_stage import ALUInputStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.branch.br_input_record import CompBROpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py
index 5ca9481db27638ee93161fb0ca8d80d64d1b6893..804643df5a01160c6996bae3fe7d8c89133ecf16 100644 (file)
--- a/src/soc/fu/branch/formal/proof_main_stage.py
+++ b/src/soc/fu/branch/formal/proof_main_stage.py
@@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.logical.main_stage import LogicalMainStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.logical.main_stage import LogicalMainStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/branch/input_stage.py b/src/soc/fu/branch/input_stage.py
index e6ab48ea32dba22bf55831b33b42891118b524e1..e0f1b34bb549838be8d0ed25754b24a9b92eea9a 100644 (file)
--- a/src/soc/fu/branch/input_stage.py
+++ b/src/soc/fu/branch/input_stage.py
@@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
 from soc.decoder.power_enums import InternalOp
-from soc.alu.pipe_data import ALUInputData
+from soc.fu.alu.pipe_data import ALUInputData
 from soc.decoder.power_enums import CryIn
 
 

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index 6f6d488adffd6292bc3aea97059bb2c33b05f10b..76b00ea06e2af9b9989fe868e9673ec108b2739f 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -7,7 +7,7 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.branch.pipe_data import BranchInputData, BranchOutputData
+from soc.fu.branch.pipe_data import BranchInputData, BranchOutputData
 from soc.decoder.power_enums import InternalOp
 
 from soc.decoder.power_fields import DecodeFields

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 0ef4f000fbeb44747cc846271aa8a288d3d6a45b..43852e055017a6f4685f9a9e9977abee2e3e090e 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -32,7 +32,7 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.decoder.power_decoder2 import Data
-from soc.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import IntegerData
 
 
 class BranchInputData(IntegerData):

diff --git a/src/soc/fu/branch/pipeline.py b/src/soc/fu/branch/pipeline.py
index ac132f74726370372ec1882c6e97b3b689be12b6..545b3435045aa436baf8cf83735abaaec81899be 100644 (file)
--- a/src/soc/fu/branch/pipeline.py
+++ b/src/soc/fu/branch/pipeline.py
@@ -1,6 +1,6 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
-from soc.branch.main_stage import BranchMainStage
+from soc.fu.branch.main_stage import BranchMainStage
 
 class BranchStages(PipeModBaseChain):
     def get_chain(self):

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 10d2bba20a50662668fb7ce0c5c8dced2a2162b1..898afa8d23f4c8be965de5e72bc8fd3824c3f647 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -12,9 +12,9 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
-from soc.branch.pipeline import BranchBasePipe
-from soc.branch.br_input_record import CompBROpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.branch.pipeline import BranchBasePipe
+from soc.fu.branch.br_input_record import CompBROpSubset
+from soc.fu.alu.pipe_data import ALUPipeSpec
 import random
 
 

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 67bd78ed82bb7f967d161e62a48deb0d8057d7d7..27d30731c1c13f8b5258ce3616d5227615963bfe 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -11,7 +11,7 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.cr.pipe_data import CRInputData, CROutputData
+from soc.fu.cr.pipe_data import CRInputData, CROutputData
 from soc.decoder.power_enums import InternalOp
 
 from soc.decoder.power_fields import DecodeFields

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index d56c8f3fac22fe48aee73aa34666afed7f1e292a..107a340e37211b73ac559bb1fb590058d08d302c 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -1,6 +1,6 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import IntegerData
 
 
 class CRInputData(IntegerData):

diff --git a/src/soc/fu/cr/pipeline.py b/src/soc/fu/cr/pipeline.py
index 121cdf8d2cc145869a5ef209854a3057eea51d2a..050d0244e725ff94bb795b67bf2a3c96498d9bd3 100644 (file)
--- a/src/soc/fu/cr/pipeline.py
+++ b/src/soc/fu/cr/pipeline.py
@@ -1,6 +1,6 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
-from soc.cr.main_stage import CRMainStage
+from soc.fu.cr.main_stage import CRMainStage
 
 class CRStages(PipeModBaseChain):
     def get_chain(self):

diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py
index fa08fb66a2613c494bda4715fd5d77c8290f2e31..0ee5977dc343669c34f3fae72b3a80ef031d52bd 100644 (file)
--- a/src/soc/fu/cr/test/test_pipe_caller.py
+++ b/src/soc/fu/cr/test/test_pipe_caller.py
@@ -12,9 +12,9 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
-from soc.cr.pipeline import CRBasePipe
-from soc.alu.alu_input_record import CompALUOpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.cr.pipeline import CRBasePipe
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.pipe_data import ALUPipeSpec
 import random
 
 

diff --git a/src/soc/fu/logical/formal/proof_bperm.py b/src/soc/fu/logical/formal/proof_bperm.py
index da198940f75b3868ca864f1d75c6e99c55b1f073..02d63cb8a4ec672b4b2878c5d7c18cd2cdbd8137 100644 (file)
--- a/src/soc/fu/logical/formal/proof_bperm.py
+++ b/src/soc/fu/logical/formal/proof_bperm.py
@@ -7,7 +7,7 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.logical.bperm import Bpermd
+from soc.fu.logical.bperm import Bpermd
 
 import unittest
 

diff --git a/src/soc/fu/logical/formal/proof_input_stage.py b/src/soc/fu/logical/formal/proof_input_stage.py
index bb62fb67c5a392c824e8afaf8b97e90723d88377..dedf33f6bf16ca84991a38341208f63fd364cc45 100644 (file)
--- a/src/soc/fu/logical/formal/proof_input_stage.py
+++ b/src/soc/fu/logical/formal/proof_input_stage.py
@@ -6,9 +6,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.alu.input_stage import ALUInputStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.input_stage import ALUInputStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/logical/formal/proof_main_stage.py b/src/soc/fu/logical/formal/proof_main_stage.py
index 5ca9481db27638ee93161fb0ca8d80d64d1b6893..804643df5a01160c6996bae3fe7d8c89133ecf16 100644 (file)
--- a/src/soc/fu/logical/formal/proof_main_stage.py
+++ b/src/soc/fu/logical/formal/proof_main_stage.py
@@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.logical.main_stage import LogicalMainStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.logical.main_stage import LogicalMainStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/logical/input_stage.py b/src/soc/fu/logical/input_stage.py
index e6ab48ea32dba22bf55831b33b42891118b524e1..e0f1b34bb549838be8d0ed25754b24a9b92eea9a 100644 (file)
--- a/src/soc/fu/logical/input_stage.py
+++ b/src/soc/fu/logical/input_stage.py
@@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
 from soc.decoder.power_enums import InternalOp
-from soc.alu.pipe_data import ALUInputData
+from soc.fu.alu.pipe_data import ALUInputData
 from soc.decoder.power_enums import CryIn
 
 

diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py
index e740d07a55c515a8fc886eb6a6a9252515baa8f4..39c2400dd718e8ae6ff24acc805ecb10af36b4dd 100644 (file)
--- a/src/soc/fu/logical/main_stage.py
+++ b/src/soc/fu/logical/main_stage.py
@@ -7,8 +7,8 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.logical.pipe_data import ALUInputData
-from soc.alu.pipe_data import ALUOutputData
+from soc.fu.logical.pipe_data import ALUInputData
+from soc.fu.alu.pipe_data import ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
 from soc.countzero.countzero import ZeroCounter

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 4bf064fe901a31f029c3f8eb0145c2f941a9c9a4..65233fde69c58f80ecf651e9d1c23189b68b8f04 100644 (file)
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,6 +1,6 @@
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import IntegerData
 
 
 class ALUInputData(IntegerData):

diff --git a/src/soc/fu/logical/pipeline.py b/src/soc/fu/logical/pipeline.py
index f3c83276ee4e437b92a7f328fa23aaff45fdbd52..1a2fd1fcc17d76a8d48525f509a9fe6331e99421 100644 (file)
--- a/src/soc/fu/logical/pipeline.py
+++ b/src/soc/fu/logical/pipeline.py
@@ -1,8 +1,8 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
-from soc.alu.input_stage import ALUInputStage
-from soc.logical.main_stage import LogicalMainStage
-from soc.alu.output_stage import ALUOutputStage
+from soc.fu.alu.input_stage import ALUInputStage
+from soc.fu.logical.main_stage import LogicalMainStage
+from soc.fu.alu.output_stage import ALUOutputStage
 
 class LogicalStages(PipeModBaseChain):
     def get_chain(self):

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 79c1e291b6d8ec1fa55d99ef82f8777832978c13..d414997e2e96a3e6b341814228ff662d3eea9e64 100644 (file)
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -12,9 +12,9 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
-from soc.logical.pipeline import LogicalBasePipe
-from soc.alu.alu_input_record import CompALUOpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.logical.pipeline import LogicalBasePipe
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.pipe_data import ALUPipeSpec
 import random
 
 

diff --git a/src/soc/fu/shift_rot/formal/proof_main_stage.py b/src/soc/fu/shift_rot/formal/proof_main_stage.py
index 50264d5c33d2f73078f13e45cd46e6381a62fe79..d390c50122e137c469cf3c4b6e2cb3b0b2bc07b7 100644 (file)
--- a/src/soc/fu/shift_rot/formal/proof_main_stage.py
+++ b/src/soc/fu/shift_rot/formal/proof_main_stage.py
@@ -7,9 +7,9 @@ from nmigen.asserts import Assert, AnyConst, Assume, Cover
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 
-from soc.shift_rot.main_stage import ShiftRotMainStage
-from soc.alu.pipe_data import ALUPipeSpec
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.shift_rot.main_stage import ShiftRotMainStage
+from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.decoder.power_enums import InternalOp
 import unittest
 

diff --git a/src/soc/fu/shift_rot/input_stage.py b/src/soc/fu/shift_rot/input_stage.py
index 72e4c9257540e33abf92c55fedfd6ae734cf3781..dde412969f9e42b47b1cdaef09f5cc9c630dd239 100644 (file)
--- a/src/soc/fu/shift_rot/input_stage.py
+++ b/src/soc/fu/shift_rot/input_stage.py
@@ -6,7 +6,7 @@ from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
                     unsigned)
 from nmutil.pipemodbase import PipeModBase
 from soc.decoder.power_enums import InternalOp
-from soc.shift_rot.pipe_data import ShiftRotInputData
+from soc.fu.shift_rot.pipe_data import ShiftRotInputData
 from soc.decoder.power_enums import CryIn
 
 

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index f237528397b0cea040266eaca4b21e1b66b1cad6..a837fb8ae3d090dd09bce62ebfbfd3a450e9bd4b 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -4,11 +4,11 @@
 # output stage
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
-from soc.alu.pipe_data import ALUOutputData
-from soc.shift_rot.pipe_data import ShiftRotInputData
+from soc.fu.alu.pipe_data import ALUOutputData
+from soc.fu.shift_rot.pipe_data import ShiftRotInputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
-from soc.shift_rot.rotator import Rotator
+from soc.fu.shift_rot.rotator import Rotator
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 7f98d16b136f121c0c73b3e8cb81d44c8457dbcc..42b70db6f3c6487821a27eafd152b014c6328cdf 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -1,8 +1,8 @@
 from nmigen import Signal, Const
 from nmutil.dynamicpipe import SimpleHandshakeRedir
-from soc.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.alu_input_record import CompALUOpSubset
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import IntegerData
 
 
 class ShiftRotInputData(IntegerData):

diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py
index 1080aa8debdaa56c571b8ab43c7638d080cfd92b..316fb832918c4df0ac6828f29e2c339d3044ac7b 100644 (file)
--- a/src/soc/fu/shift_rot/pipeline.py
+++ b/src/soc/fu/shift_rot/pipeline.py
@@ -1,8 +1,8 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
-from soc.shift_rot.input_stage import ShiftRotInputStage
-from soc.shift_rot.main_stage import ShiftRotMainStage
-from soc.alu.output_stage import ALUOutputStage
+from soc.fu.shift_rot.input_stage import ShiftRotInputStage
+from soc.fu.shift_rot.main_stage import ShiftRotMainStage
+from soc.fu.alu.output_stage import ALUOutputStage
 
 class ShiftRotStages(PipeModBaseChain):
     def get_chain(self):

diff --git a/src/soc/fu/shift_rot/rotator.py b/src/soc/fu/shift_rot/rotator.py
index 23aa0e43ae86e19cbe2a949792d7c03959925c74..3079a5c74e895fb621419236e2cb7e797db48612 100644 (file)
--- a/src/soc/fu/shift_rot/rotator.py
+++ b/src/soc/fu/shift_rot/rotator.py
@@ -3,7 +3,7 @@
 
 from nmigen import (Elaboratable, Signal, Module, Const, Cat,
                     unsigned, signed)
-from soc.shift_rot.rotl import ROTL
+from soc.fu.shift_rot.rotl import ROTL
 
 # note BE bit numbering
 def right_mask(m, mask_begin):

diff --git a/src/soc/fu/shift_rot/test/test_maskgen.py b/src/soc/fu/shift_rot/test/test_maskgen.py
index 1a4d34e676154b250f95ef120932a9b88fcaf937..93f38f2471a0f8098c4e39a6a682285b393e389e 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_maskgen.py
+++ b/src/soc/fu/shift_rot/test/test_maskgen.py
@@ -2,7 +2,7 @@ from nmigen import Signal, Module
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
-from soc.alu.maskgen import MaskGen
+from soc.fu.alu.maskgen import MaskGen
 from soc.decoder.helpers import MASK
 import random
 import unittest

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index dbd4092395cb85a3d3158c5047a14f1a76786ba2..def0256cef2aa18be381dd46945d4084e1f2bf2b 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -12,9 +12,9 @@ from soc.simulator.program import Program
 from soc.decoder.isa.all import ISA
 
 
-from soc.shift_rot.pipeline import ShiftRotBasePipe
-from soc.alu.alu_input_record import CompALUOpSubset
-from soc.alu.pipe_data import ALUPipeSpec
+from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
+from soc.fu.alu.alu_input_record import CompALUOpSubset
+from soc.fu.alu.pipe_data import ALUPipeSpec
 import random
 
 class TestCase: