add bc ctr regression test when CTR=0 and CTR=1

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 028fcd381241baa91833273ddd17bf7ae392e819..8862e22c843262fc7b74ea6949d83058956e279a 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -400,7 +400,7 @@ class ISACaller:
             # these are all opcode fields involved in index-selection of CR,
             # and need to do "standard" arithmetic.  CR[BA+32] for example
             # would, if using SelectableInt, only be 5-bit.
             # these are all opcode fields involved in index-selection of CR,
             # and need to do "standard" arithmetic.  CR[BA+32] for example
             # would, if using SelectableInt, only be 5-bit.

-            if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT']:
+            if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:

                 self.namespace[name] = val
             else:
                 self.namespace[name] = SelectableInt(val, sig.width)
                 self.namespace[name] = val
             else:
                 self.namespace[name] = SelectableInt(val, sig.width)

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index a8caa144b1905f2ba0cf51e79566d95894476527..bf18db7269da4ef9ce4525b4c3b6af804a22ebc0 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -96,11 +96,15 @@ class BranchMainStage(PipeModBase):
 
         # fields for conditional branches (BO and BI are same for BC and BCREG)
         b_fields = self.fields.FormB
 
         # fields for conditional branches (BO and BI are same for BC and BCREG)
         b_fields = self.fields.FormB

-        BO = b_fields.BO[0:-1]
-        BI = b_fields.BI[0:-1][0:2] # CR0-7 selected already in PowerDecode2.
+        BO = b_fields.BO
+        BI = b_fields.BI[0:2] # CR0-7 selected already in PowerDecode2.

 
         cr_bits = Array([cr[3-i] for i in range(4)]) # invert. Because POWER.
 
 
         cr_bits = Array([cr[3-i] for i in range(4)]) # invert. Because POWER.
 

+        # copy of BO in a signal
+        bo = Signal(5, reset_less=True)
+        comb += bo.eq(BO[0:5])
+

         # The bit of CR selected by BI
         bi = Signal(2, reset_less=True)
         cr_bit = Signal(reset_less=True)
         # The bit of CR selected by BI
         bi = Signal(2, reset_less=True)
         cr_bit = Signal(reset_less=True)


@@ -113,8 +117,8 @@ class BranchMainStage(PipeModBase):
 
         # Whether the conditional branch should be taken
         bc_taken = Signal(reset_less=True)
 
         # Whether the conditional branch should be taken
         bc_taken = Signal(reset_less=True)

-        with m.If(BO[2]):
-            comb += bc_taken.eq((cr_bit == BO[3]) | BO[4])
+        with m.If(bo[2]):
+            comb += bc_taken.eq((cr_bit == bo[3]) | bo[4])

         with m.Else():
             # decrement the counter and place into output
             ctr_n = Signal(64, reset_less=True)
         with m.Else():
             # decrement the counter and place into output
             ctr_n = Signal(64, reset_less=True)


@@ -127,14 +131,14 @@ class BranchMainStage(PipeModBase):
                 comb += ctr_m.eq(ctr[:32])
             with m.Else():
                 comb += ctr_m.eq(ctr)
                 comb += ctr_m.eq(ctr[:32])
             with m.Else():
                 comb += ctr_m.eq(ctr)

-            # check CTR zero/non-zero against BO[1]
-            ctr_zero_bo1 = Signal(reset_less=True) # BO[1] == (ctr==0)
-            comb += ctr_zero_bo1.eq(BO[1] ^ ctr_m.any())
-            with m.If(BO[3:5] == 0b00):
+            # check CTR zero/non-zero against bo[1]
+            ctr_zero_bo1 = Signal(reset_less=True) # bo[1] == (ctr==0)
+            comb += ctr_zero_bo1.eq(bo[1] ^ ctr_n.any())
+            with m.If(bo[3:5] == 0b00):

                 comb += bc_taken.eq(ctr_zero_bo1 & ~cr_bit)
                 comb += bc_taken.eq(ctr_zero_bo1 & ~cr_bit)

-            with m.Elif(BO[3:5] == 0b01):
+            with m.Elif(bo[3:5] == 0b01):

                 comb += bc_taken.eq(ctr_zero_bo1 & cr_bit)
                 comb += bc_taken.eq(ctr_zero_bo1 & cr_bit)

-            with m.Elif(BO[4] == 1):
+            with m.Elif(bo[4] == 1):

                 comb += bc_taken.eq(ctr_zero_bo1)
 
         ### Main Switch Statement ###
                 comb += bc_taken.eq(ctr_zero_bo1)
 
         ### Main Switch Statement ###

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 54d88476bf686309ff60dbc9a36d8c1acfa0626f..0376a74ecc1e6d95790e7616855df7a04061c173 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -106,6 +106,30 @@ class BranchTestCase(TestAccumulatorBase):
                               initial_sprs=initial_sprs,
                               initial_cr=cr)
 
                               initial_sprs=initial_sprs,
                               initial_cr=cr)
 

+    def case_bc_microwatt_1_regression(self):
+        """bc found to be testing ctr rather than (ctr-1)
+        11fb4:   08 00 49 40     bc      2,4*cr2+gt,0x11fbc
+        cr_file.vhdl:83:13:@136835ns:(report note): Reading CR 33209703
+        """
+        lst = ["bc 2, 9, 8"]
+        initial_regs = [0] * 32
+        cr = 0x33209703
+        self.add_case(Program(lst, bigendian), initial_regs,
+                              initial_cr=cr)
+
+    def case_bc_microwatt_2_regression(self):
+        """modified version, set CTR=1 so that it hits zero in BC
+        """
+        lst = ["bc 2, 9, 8"]
+        initial_regs = [0] * 32
+        cr = 0x33209703
+        ctr = 1
+        initial_sprs = {9: SelectableInt(ctr, 64),
+                        }
+        self.add_case(Program(lst, bigendian), initial_regs,
+                              initial_sprs=initial_sprs,
+                              initial_cr=cr)
+

     def case_ilang(self):
         pspec = BranchPipeSpec(id_wid=2)
         alu = BranchBasePipe(pspec)
     def case_ilang(self):
         pspec = BranchPipeSpec(id_wid=2)
         alu = BranchBasePipe(pspec)

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 4fee28f4e5aa1acbfe48ee753aebd39249c40426..13e41029ae48dce8a8ca0e30f58f635032aff380 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -308,7 +308,7 @@ class LibreSoCSim(SoCSDRAM):
         )
 
         if cpu == "libresoc":
         )
 
         if cpu == "libresoc":

-            self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x11700))
+            self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12000))

             #self.comb += active_dbg_cr.eq(1)
 
             # get the CR
             #self.comb += active_dbg_cr.eq(1)
 
             # get the CR