start adding svp64 enums

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 51cd94bbdfb22839d1a5d74ef8a647f8e3941ff9..74c149e3b5cc5e45d8212b879ebb8ce74128be2e 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -1,3 +1,7 @@
+# SPDX-License: LGPLv3+
+# Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+# Copyright (C) 2020, Michael Nolan
+

 from enum import Enum, unique
 import csv
 import os
 from enum import Enum, unique
 import csv
 import os


@@ -65,6 +69,7 @@ class Function(Enum):
     DIV = 1 << 9
     SPR = 1 << 10
     MMU = 1 << 11
     DIV = 1 << 9
     SPR = 1 << 10
     MMU = 1 << 11

+    SV = 1 << 12 # Simple-V https://libre-soc.org/openpower/sv

 
 
 @unique
 
 
 @unique


@@ -99,6 +104,19 @@ class Form(Enum):
     Z22 = 27
     Z23 = 28
 
     Z22 = 27
     Z23 = 28
 

+# Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
+
+@unique
+class SVPtype(Enum):
+    NONE = 0
+    P1 = 1
+    P2 = 2
+
+@unique
+class SVEtype(Enum):
+    NONE = 0
+    EXTRA2 = 1
+    EXTRA3 = 2

 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else


@@ -123,7 +141,9 @@ _insns = [
     "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
     "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
     "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
     "nand", "neg", "nego", "nop", "nor", "or", "orc", "ori", "oris",
     "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
     "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",

-    "rlwnm", "setb", "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
+    "rlwnm", "setb",
+    "setvl", # https://libre-soc.org/openpower/sv/setvl
+    "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",

     "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
     "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",
     "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
     "sthu", "sthux", "sthx", "stw", "stwbrx", "stwcx", "stwu", "stwux",

diff --git a/src/soc/decoder/power_svp64.py b/src/soc/decoder/power_svp64.py
index 32498f954566d25cde49a688ad0bcac248067ba7..8bb896afcd11664edba15c42ffd93e6980df6557 100644 (file)
--- a/src/soc/decoder/power_svp64.py
+++ b/src/soc/decoder/power_svp64.py
@@ -128,6 +128,13 @@ class SVP64RM:
             cr_out = entry['CR out']
             entry['sv_cr_out'] = svp64_dest.get(cr_out, None)
 
             cr_out = entry['CR out']
             entry['sv_cr_out'] = svp64_dest.get(cr_out, None)
 

+            # more enum-friendly Ptype names.  should have done this in
+            # sv_analysis.py, oh well
+            if entry['SV_Ptype'] == '1P':
+                if entry['SV_Ptype'] = 'P1'
+            if entry['SV_Ptype'] == '2P':
+                if entry['SV_Ptype'] = 'P2'
+

         return v30b
 
 if __name__ == '__main__':
         return v30b
 
 if __name__ == '__main__':