create a special subset of Decoder Record for storing "main" decoder info

this has to store Trap info however everything else is optional

diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py
index f9aa722daaf1045699d8b4116bdfdd74807b2630..cd4285be533d2c182a5c5102dda07940bee43bfe 100644 (file)
--- a/src/soc/decoder/decode2execute1.py
+++ b/src/soc/decoder/decode2execute1.py
@@ -24,7 +24,14 @@ class Data(Record):
         return [self.data, self.ok]
 
 
-class Decode2ToOperand(RecordObject):
+class IssuerDecode2ToOperand(RecordObject):
+    """IssuerDecode2ToOperand
+
+    contains the subset of fields needed for Issuer to decode the instruction
+    and get register rdflags signals set up.  it also doubles up as the
+    "Trap" temporary store, because part of the Decoder's job is to
+    identify whether a trap / interrupt / exception should occur.
+    """
 
     def __init__(self, name=None):
 
@@ -38,13 +45,27 @@ class Decode2ToOperand(RecordObject):
         self.insn = Signal(32, reset_less=True) # original instruction
         self.insn_type = Signal(MicrOp, reset_less=True)
         self.fn_unit = Signal(Function, reset_less=True)
-        self.imm_data = Data(64, name="imm")
         self.lk = Signal(reset_less=True)
         self.rc = Data(1, "rc")
         self.oe = Data(1, "oe")
+        self.input_carry = Signal(CryIn, reset_less=True)
+        self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
+        self.trapaddr  = Signal(13, reset_less=True)
+        self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
+        self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
+        self.is_32bit = Signal(reset_less=True)
+
+
+class Decode2ToOperand(IssuerDecode2ToOperand):
+
+    def __init__(self, name=None):
+
+        IssuerDecode2ToOperand.__init__(self, name=name)
+
+        # instruction, type and decoded information
+        self.imm_data = Data(64, name="imm")
         self.invert_in = Signal(reset_less=True)
         self.zero_a = Signal(reset_less=True)
-        self.input_carry = Signal(CryIn, reset_less=True)
         self.output_carry = Signal(reset_less=True)
         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
@@ -55,10 +76,6 @@ class Decode2ToOperand(RecordObject):
         self.byte_reverse  = Signal(reset_less=True)
         self.sign_extend  = Signal(reset_less=True)# do we need this?
         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
-        self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
-        self.trapaddr  = Signal(13, reset_less=True)
-        self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
-        self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
         self.write_cr0 = Signal(reset_less=True)
 
 
@@ -97,4 +114,5 @@ class Decode2ToExecute1Type(RecordObject):
 
         # decode operand data
         print ("decode2execute init", name, opkls)
+        #assert name is not None, str(opkls)
         self.do = opkls(name)

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 389c98b58aefb79ad6dfc26031f84d4fe3841a44..45918668ba8b5f318cb7e5b2c8606e05f670ed17 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -602,14 +602,13 @@ class PowerDecodeSubset(Elaboratable):
                             final=False, state=None):
 
         self.final = final
+        self.opkls = opkls
         if dec is None:
-            self.opkls = opkls
             self.fn_name = fn_name
             self.dec = create_pdecode(name=fn_name, col_subset=col_subset,
                                       row_subset=self.rowsubsetfn)
         else:
             self.dec = dec
-            self.opkls = None
             self.fn_name = None
         self.e = Decode2ToExecute1Type(name=self.fn_name, opkls=self.opkls)
 

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index d102b56de3ed089e3d3a5aafae74e4d811bc8281..f83e4b8ce7f306d4f7f318b157a5a9d3eab758e9 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -53,16 +53,16 @@ class LibreSoCSim(SoCSDRAM):
 
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
-        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/3.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/1.bin"
         #ram_fname = "/tmp/test.bin"
         #ram_fname = None
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "micropython/firmware.bin"
-        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-        #            "tests/xics/xics.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/decrementer/decrementer.bin"
+                    "tests/xics/xics.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
 

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 6f9c2a86b4087b9f12d033f01536cf718080d209..3a9b5a899f832facc0c04e774e7261b0de3e451b 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -32,6 +32,7 @@ from nmutil.util import treereduce
 from soc.fu.compunits.compunits import AllFunctionUnits
 from soc.regfile.regfiles import RegFiles
 from soc.decoder.decode2execute1 import Decode2ToExecute1Type
+from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
 from soc.decoder.power_decoder2 import get_rdflags
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
@@ -79,8 +80,9 @@ class NonProductionCore(Elaboratable):
         # register files (yes plural)
         self.regs = RegFiles()
 
-        # instruction decoder
-        self.e = Decode2ToExecute1Type("core") # decoded instruction
+        # instruction decoder - needs a Trap-capable Record (captures EINT etc.)
+        self.e = Decode2ToExecute1Type("core", opkls=IssuerDecode2ToOperand)
+
         self.state = CoreState("core")
         self.raw_insn_i = Signal(32) # raw instruction
         self.bigendian_i = Signal() # bigendian

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index eec9bc5007ed5fa180503b4f9e880bf3f90723fd..f0b2b1bf30344b188198832f1da7b4157f142ec7 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -23,6 +23,7 @@ import sys
 
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
+from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
 from soc.decoder.decode2execute1 import Data
 from soc.experiment.testmem import TestMemory # test only for instructions
 from soc.regfile.regfiles import StateRegs, FastRegs
@@ -58,13 +59,14 @@ class TestIssuer(Elaboratable):
             self.simple_gpio = SimpleGPIO()
             self.gpio_o = self.simple_gpio.gpio_o
 
-        # main instruction core
+        # main instruction core25
         self.core = core = NonProductionCore(pspec)
 
-        # instruction decoder
+        # instruction decoder.  goes into Trap Record
         pdecode = create_pdecode()
         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
-        self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state)
+        self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
+                                     opkls=IssuerDecode2ToOperand)
 
         # Test Instruction memory
         self.imem = ConfigFetchUnit(pspec).fu