remove vhdl comments

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index 7a7ea14691f0c24026c4edce92f0d7cbbe465fbc..47aa0f8568c06f8a80c2ab262bb9eb21b6263076 100644 (file)
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -7,18 +7,6 @@ from nmutil.iocontrol import RecordObject
 from nmigen import Signal
 
 
-# type Loadstore1ToMmuType is record
-#     valid : std_ulogic;
-#     tlbie : std_ulogic;
-#     slbia : std_ulogic;
-#     mtspr : std_ulogic;
-#     iside : std_ulogic;
-#     load  : std_ulogic;
-#     priv  : std_ulogic;
-#     sprn  : std_ulogic_vector(9 downto 0);
-#     addr  : std_ulogic_vector(63 downto 0);
-#     rs    : std_ulogic_vector(63 downto 0);
-#  end record;
 class LoadStore1ToMmuType(RecordObject):
     def __init__(self):
         super().__init__()
@@ -33,16 +21,7 @@ class LoadStore1ToMmuType(RecordObject):
         self.addr  = Signal(64)
         self.rs    = Signal(64)
 
-# type MmuToLoadstore1Type is record
-#     done       : std_ulogic;
-#     err        : std_ulogic;
-#     invalid    : std_ulogic;
-#     badtree    : std_ulogic;
-#     segerr     : std_ulogic;
-#     perm_error : std_ulogic;
-#     rc_error   : std_ulogic;
-#     sprval     : std_ulogic_vector(63 downto 0);
-# end record;
+
 class MmuToLoadStore1Type(RecordObject):
     def __init__(self):
         super().__init__()
@@ -55,14 +34,7 @@ class MmuToLoadStore1Type(RecordObject):
         self.rc_error   = Signal()
         self.sprval     = Signal(64)
 
-# type MmuToDcacheType is record
-#     valid : std_ulogic;
-#     tlbie : std_ulogic;
-#     doall : std_ulogic;
-#     tlbld : std_ulogic;
-#     addr  : std_ulogic_vector(63 downto 0);
-#     pte   : std_ulogic_vector(63 downto 0);
-# end record;
+
 class MmuToDcacheType(RecordObject):
     def __init__(self):
         super().__init__()
@@ -73,12 +45,7 @@ class MmuToDcacheType(RecordObject):
         self.addr  = Signal(64)
         self.pte   = Signal(64)
 
-# type DcacheToMmuType is record
-#     stall : std_ulogic;
-#     done  : std_ulogic;
-#     err   : std_ulogic;
-#     data  : std_ulogic_vector(63 downto 0);
-# end record;
+
 class DcacheToMmuType(RecordObject):
     def __init__(self):
         super().__init__()
@@ -88,13 +55,7 @@ class DcacheToMmuType(RecordObject):
         self.data  = Signal(64)
 
 
-# type MmuToIcacheType is record
-#    tlbld : std_ulogic;
-#    tlbie : std_ulogic;
-#    doall : std_ulogic;
-#    addr  : std_ulogic_vector(63 downto 0);
-#    pte   : std_ulogic_vector(63 downto 0);
-# end record;
+
 class MmuToIcacheType(RecordObject):
     def __init__(self):
         super().__init__()
@@ -104,18 +65,7 @@ class MmuToIcacheType(RecordObject):
         self.addr  = Signal(64)
         self.pte   = Signal(64)
 
-# type Loadstore1ToDcacheType is record
-#     valid     : std_ulogic;
-#     load      : std_ulogic; -- is this a load
-#     dcbz      : std_ulogic;
-#     nc        : std_ulogic;
-#     reserve   : std_ulogic;
-#     virt_mode : std_ulogic;
-#     priv_mode : std_ulogic;
-#     addr      : std_ulogic_vector(63 downto 0);
-#     data      : std_ulogic_vector(63 downto 0);
-#     byte_sel  : std_ulogic_vector(7 downto 0);
-# end record;
+
 class LoadStore1ToDcacheType(RecordObject):
     def __init__(self):
         super().__init__()
@@ -131,13 +81,7 @@ class LoadStore1ToDcacheType(RecordObject):
         self.data      = Signal()
         self.byte_sel  = Signal()
 
-# type DcacheToLoadstore1Type is record
-#     valid         : std_ulogic;
-#     data          : std_ulogic_vector(63 downto 0);
-#     store_done    : std_ulogic;
-#     error         : std_ulogic;
-#     cache_paradox : std_ulogic;
-# end record;
+
 class DcacheToLoadStore1Type(RecordObject):
     def __init__(self):
         super().__init__()