oops forgot to switch write-enable off

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index c1bbf7438664f65adb570f006b5fb085700c09d3..ed688a48d3ef6fed4e2eef6fd489e57edacb6c50 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -164,6 +164,8 @@ class NonProductionCore(Elaboratable):
                 # will the write-enable be activated
                 with m.If(wrpick.en_o):
                     sync += wport.wen.eq(write)
+                with m.Else():
+                    sync += wport.wen.eq(0)
 
                 # connect up the FU req/go signals and the reg-read to the FU
                 # these are arbitrated by Data.ok signals