add simple GPIO peripheral to verilog TestIssuer

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index a60bf38a4a4744580d0e5eb6145bd01ecef2048d..17ca9df6ac61c42537c9f8183118f0114dc60913 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -33,6 +33,7 @@ from soc.decoder.power_enums import MicrOp
 from soc.debug.dmi import CoreDebug, DMIInterface
 from soc.config.state import CoreState
 from soc.interrupts.xics import XICS_ICP, XICS_ICS
+from soc.bus.simple_gpio import SimpleGPIO
 
 from nmutil.util import rising_edge
 
@@ -51,6 +52,12 @@ class TestIssuer(Elaboratable):
             self.xics_ics = XICS_ICS()
             self.int_level_i = self.xics_ics.int_level_i
 
+        # add GPIO peripheral?
+        self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
+        if self.gpio:
+            self.simple_gpio = SimpleGPIO()
+            self.gpio_o = self.simple_gpio.gpio_o
+
         # main instruction core
         self.core = core = NonProductionCore(pspec)
 
@@ -100,12 +107,21 @@ class TestIssuer(Elaboratable):
         m.submodules.imem = imem = self.imem
         m.submodules.dbg = dbg = self.dbg
 
+        # XICS interrupt handler
         if self.xics:
             m.submodules.xics_icp = icp = self.xics_icp
             m.submodules.xics_ics = ics = self.xics_ics
             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
             comb += core.ext_irq_i.eq(icp.core_irq_o) # connect ICP to core
 
+        # GPIO test peripheral
+        if self.gpio:
+            m.submodules.simple_gpio = simple_gpio = self.simple_gpio
+
+        # connect one GPIO output to ICS bit 5 (like in microwatt soc.vhdl)
+        if self.gpio and self.xics:
+            comb += self.int_level_i[5].eq(simple_gpio.gpio_o[0])
+
         # instruction decoder
         pdecode = create_pdecode()
         m.submodules.dec2 = pdecode2 = self.pdecode2
@@ -328,6 +344,10 @@ class TestIssuer(Elaboratable):
             ports += list(self.xics_ics.bus.fields.values())
             ports.append(self.int_level_i)
 
+        if self.gpio:
+            ports += list(self.simple_gpio.bus.fields.values())
+            ports.append(self.gpio_o)
+
         return ports
 
     def ports(self):

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 1f7c7b370a90f5a98a131f551122d41f658fb6a4..854c0981410c617b0fd5a79743c4a3b70d6b13ba 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,6 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
+                         gpio=True, # for test purposes
                          units=units)
     dut = TestIssuer(pspec)