remove unneeded imports

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index c10e95843f336ace66e4861c90d4500ed758e768..350b4b82a46d0d064f4ac6cd0329e60c00bb7952 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -10,13 +10,12 @@ its result(s) have been successfully stored in the regfile(s)
 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
 """
 
-from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Cat, Const
+from nmigen import Module, Signal, Mux, Elaboratable, Repl, Cat, Const
 from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT)
 
 from nmutil.latch import SRLatch, latchregister
 from nmutil.iocontrol import RecordObject
 
-from soc.decoder.power_decoder2 import Data
 from soc.fu.regspec import RegSpec, RegSpecALUAPI
 
 

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index f0873ba6bd53616341433da3a3431d665030e4ac..f794ad98aa8259fbcc4b8c7fb9329b5857a6b40d 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -11,16 +11,10 @@ Documented at http://libre-soc.org/3d_gpu/architecture/compunit
 """
 
 from nmigen.compat.sim import run_simulation, Settle
-from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Mux, Elaboratable, Repl, Array, Cat, Const
-from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT)
+from nmigen.cli import rtlil
+from nmigen import Module
 
-from nmutil.latch import SRLatch, latchregister
-from nmutil.iocontrol import RecordObject
-
-from soc.decoder.power_decoder2 import Data
 from soc.decoder.power_enums import InternalOp
-from soc.fu.regspec import RegSpec, RegSpecALUAPI
 
 from soc.experiment.compalu_multi import MultiCompUnit
 from soc.experiment.alu_hier import ALU, DummyALU