The old regspec API can't cope with different port sizes.
The CR port is now changed from 3 to "width" bits (16).
The problem was that cr.ok went into the fourth bit, messing with
the results.
self.a, self.b = i[0], i[1]
out = []
out.append(Data(width, name="alu_o"))
self.a, self.b = i[0], i[1]
out = []
out.append(Data(width, name="alu_o"))
- out.append(Data(3, name="alu_cr"))
+ out.append(Data(width, name="alu_cr"))
self.out = Array(out)
self.o = self.out[0]
self.cr = self.out[1]
self.out = Array(out)
self.o = self.out[0]
self.cr = self.out[1]
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]
outspec = [('INT', 'o', '0:15'),
inspec = [('INT', 'a', '0:15'),
('INT', 'b', '0:15')]
outspec = [('INT', 'o', '0:15'),
regspec = (inspec, outspec)
regspec = (inspec, outspec)