Add external access to table size to plru

diff --git a/TLB/src/ariane/plru.py b/TLB/src/ariane/plru.py
index c8b26031b636e4fb23b9378354e0400fee16f0a2..50951c1f58e59b7ad2701007e4d282e13a51f7a4 100644 (file)
--- a/TLB/src/ariane/plru.py
+++ b/TLB/src/ariane/plru.py
@@ -22,8 +22,8 @@ class PLRU:
         self.replace_en_o = Signal(entries)
         self.lu_access_i = Signal()
         # Tree (bit per entry)
-        TLBSZ = 2*(self.entries-1)
-        self.plru_tree = Signal(TLBSZ)
+        self.TLBSZ = 2*(self.entries-1)
+        self.plru_tree = Signal(self.TLBSZ)
 
     def elaborate(self, platform):
         m = Module()