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test_issuer_mmu_data_path.py: test both ld and st instructions
author
Tobias Platen
<tplaten@posteo.de>
Tue, 19 Jan 2021 18:54:45 +0000
(19:54 +0100)
committer
Tobias Platen
<tplaten@posteo.de>
Tue, 19 Jan 2021 18:54:45 +0000
(19:54 +0100)
src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
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diff --git
a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index 88d9b6b153e568610676bf9378b2024ccd1b60d5..f6208229a4ea89bd909440c6881f0c4c748aaec2 100644
(file)
--- a/
src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/
src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@
-13,19
+13,20
@@
class MMUTestCase(TestAccumulatorBase):
# libre-soc has own SPR unit
# other instructions here -> must be load/store
# libre-soc has own SPR unit
# other instructions here -> must be load/store
- def case_m
fspr_after_invalid_load
(self):
+ def case_m
mu_ldst
(self):
lst = [
"dcbz 1,2",
"tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
#"mfspr 1, 18", # DSISR to reg 1
#"mfspr 2, 19", # DAR to reg 2
lst = [
"dcbz 1,2",
"tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
#"mfspr 1, 18", # DSISR to reg 1
#"mfspr 2, 19", # DAR to reg 2
- #"mtspr 18, 1",
- #"mtspr 19, 2",
- #
test ldst instructions
- "lhz 3, 0(1)"
# lhz RT,D(RA) -> this should go through the mmu
+ #"mtspr 18, 1",
# TODO
+ #"mtspr 19, 2",
# TODO
+ #
"std 1, 0(2)"
+ "lhz 3, 0(1)"
# load some data
]
initial_regs = [0] * 32
]
initial_regs = [0] * 32
+ #initial_regs[1] = 0xDEADBEEF
#FIXME initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
initial_sprs = {}
#FIXME initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
initial_sprs = {}