add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer if enabled

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index aa7fe20a24c2b610befed6f34687057a9f134e43..d86b237508152d9555fb8317d929e84fd605e74f 100644 (file)
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -12,7 +12,7 @@ class SPBlock512W64B8W(Elaboratable):
     Instance SPBlock512W64B8W).  512 rows, 64-bit, QTY 8 write-enable lines
     """
 
-    def __init__(self, bus=None, features=None):
+    def __init__(self, bus=None, features=None, name=None):
         if features is None:
             features = frozenset()
         if bus is None:
@@ -21,7 +21,7 @@ class SPBlock512W64B8W(Elaboratable):
                             granularity=8, # at 8-bit granularity
                             features=features,
                             alignment=0,
-                            name=None)
+                            name=name)
         self.bus = bus
         self.granularity = bus.granularity
 

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 42fb54c657bd9f396e3355bd6154e8959509e3f7..ceec6f352452982bdb64cd33f437cd12a73d020d 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -37,6 +37,7 @@ from soc.config.pinouts import get_pinspecs
 from soc.config.state import CoreState
 from soc.interrupts.xics import XICS_ICP, XICS_ICS
 from soc.bus.simple_gpio import SimpleGPIO
+from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
 from soc.clock.select import ClockSelect
 from soc.clock.dummypll import DummyPLL
 from soc.sv.svstate import SVSTATERec
@@ -75,6 +76,14 @@ class TestIssuerInternal(Elaboratable):
             pspec.wb_icache_en = self.jtag.wb_icache_en
             pspec.wb_dcache_en = self.jtag.wb_dcache_en
 
+        # add 4k sram blocks?
+        self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and 
+                         pspec.sram4x4kblock == True)
+        if self.sram4x4k:
+            self.sram4k = []
+            for i in range(4):
+                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
+
         # add interrupt controller?
         self.xics = hasattr(pspec, "xics") and pspec.xics == True
         if self.xics:
@@ -149,6 +158,11 @@ class TestIssuerInternal(Elaboratable):
 
         cur_state = self.cur_state
 
+        # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
+        if self.sram4x4k:
+            for i, sram in enumerate(self.sram4k):
+                m.submodules["sram4k_%d" % i] = sram
+
         # XICS interrupt handler
         if self.xics:
             m.submodules.xics_icp = icp = self.xics_icp
@@ -537,6 +551,10 @@ class TestIssuerInternal(Elaboratable):
         ports += list(self.imem.ibus.fields.values())
         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 
+        if self.sram4x4k:
+            for sram in self.sram4k:
+                ports += list(sram.bus.fields.values())
+
         if self.xics:
             ports += list(self.xics_icp.bus.fields.values())
             ports += list(self.xics_ics.bus.fields.values())