experimenting with PTW
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 19 Apr 2019 01:42:20 +0000 (02:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 19 Apr 2019 01:42:20 +0000 (02:42 +0100)
TLB/src/ariane/test_ptw.py

index 35581bdb6c105bd4e3deec54983fed3f458f2f02..fd5fc0ac2b57408ff5b7f3bb6ae686f239facf69 100644 (file)
@@ -44,6 +44,41 @@ def testbench(dut):
     yield
     yield
 
+    addr = 0x4000000
+    yield dut.dtlb_vaddr_i.eq(addr)
+    yield dut.mxr_i.eq(0x1)
+    yield dut.req_port_i.data_gnt.eq(1)
+    yield dut.req_port_i.data_rvalid.eq(1)
+    yield dut.req_port_i.data_rdata.eq(0x82<<56 | addr<<2)#pte.flatten())
+
+    yield dut.en_ld_st_translation_i.eq(1)
+    yield dut.asid_i.eq(1)
+
+    yield dut.dtlb_access_i.eq(1)
+    yield dut.dtlb_hit_i.eq(0)
+    yield dut.dtlb_vaddr_i.eq(addr)
+
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+
+    yield dut.req_port_i.data_gnt.eq(0)
+    yield dut.dtlb_access_i.eq(1)
+    yield dut.dtlb_hit_i.eq(0)
+    yield dut.dtlb_vaddr_i.eq(0x400000011)
+
+    yield
+    yield dut.req_port_i.data_gnt.eq(1)
+    yield
+    yield
+    yield
+    yield
+
     yield