litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default

of versa_ecp5, to build for different fpga targets, fix whitespace,
delete ulx3s85f.py as it's no longer needed

diff --git a/src/soc/litex/florent/ulx3s85f.py b/src/soc/litex/florent/ulx3s85f.py
deleted file mode 100755 (executable)
index 7801cfa..0000000
--- a/src/soc/litex/florent/ulx3s85f.py
+++ /dev/null
@@ -1,65 +0,0 @@
-#!/usr/bin/env python3
-
-import os
-import argparse
-
-from litex_boards.platforms import ulx3s
-from litex_boards.targets.ulx3s import _CRG, BaseSoC
-
-from litex.soc.integration.soc_sdram import (soc_sdram_args,
-                                             soc_sdram_argdict)
-from litex.soc.integration.builder import (Builder, builder_args,
-                                           builder_argdict)
-
-from libresoc import LibreSoC
-#from microwatt import Microwatt
-
-# TestSoC ------------------------------------------------------------------------------------------
-
-class TestSoC(BaseSoC):
-    def __init__(self, sys_clk_freq=int(16e6), **kwargs):
-        kwargs["integrated_rom_size"] = 0x10000
-        #kwargs["integrated_main_ram_size"] = 0x1000
-        kwargs["csr_data_width"] = 32
-        kwargs["l2_size"] = 0
-        #bus_data_width = 16,
-        BaseSoC.__init__(self, device="LFE5U-85F", sys_clk_freq=sys_clk_freq,
-            cpu_type    = "external",
-            cpu_cls     = LibreSoC,
-            cpu_variant = "standardjtag",
-            #cpu_cls  = Microwatt,
-            **kwargs)
-
-        #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
-        #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
-        #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
-
-        #self.add_constant("MEMTEST_BUS_DEBUG", 1)
-        #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
-        #self.add_constant("MEMTEST_DATA_DEBUG", 1)
-
-# Build --------------------------------------------------------------------------------------------
-
-def main():
-    parser = argparse.ArgumentParser(
-                description="LiteX SoC with LibreSoC CPU on ULX3S-85F")
-    parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
-    parser.add_argument("--sys-clk-freq",  default=int(16e6),
-                         help="System clock frequency (default=16MHz)")
-
-    builder_args(parser)
-    soc_sdram_args(parser)
-    args = parser.parse_args()
-
-    soc = TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
-                  **soc_sdram_argdict(args))
-    builder = Builder(soc, **builder_argdict(args))
-    builder.build(run=args.build)
-
-    if args.load:
-        prog = soc.platform.create_programmer()
-        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
-
-if __name__ == "__main__":
-    main()

diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index 55787f25094f1b97a33a888e90a4f4dfd34dfa99..e2e31d14e257c3181d11df86e5f8a6d135d3c801 100755 (executable)
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -3,8 +3,8 @@
 import os
 import argparse
 
-from litex_boards.platforms import versa_ecp5
-from litex_boards.targets.versa_ecp5 import _CRG, BaseSoC
+import litex_boards.targets.versa_ecp5 as versa_ecp5
+import litex_boards.targets.ulx3s as ulx3s
 
 from litex.soc.integration.soc_sdram import (soc_sdram_args,
                                              soc_sdram_argdict)
@@ -14,21 +14,24 @@ from litex.soc.integration.builder import (Builder, builder_args,
 from libresoc import LibreSoC
 #from microwatt import Microwatt
 
-# TestSoC ------------------------------------------------------------------------------------------
+# TestSoC
+# ----------------------------------------------------------------------------
 
-class TestSoC(BaseSoC):
+class VersaECP5TestSoC(versa_ecp5.BaseSoC):
     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
         kwargs["integrated_rom_size"] = 0x10000
         #kwargs["integrated_main_ram_size"] = 0x1000
         kwargs["csr_data_width"] = 32
         kwargs["l2_size"] = 0
         #bus_data_width = 16,
-        BaseSoC.__init__(self, sys_clk_freq,
-            cpu_type = "external",
-            cpu_cls  = LibreSoC,
-            cpu_variant = "standardjtag",
-            #cpu_cls  = Microwatt,
-            device        = "LFE5UM",
+
+        versa_ecp5.BaseSoC.__init__(self,
+            sys_clk_freq = sys_clk_freq,
+            cpu_type     = "external",
+            cpu_cls      = LibreSoC,
+            cpu_variant  = "standardjtag",
+            #cpu_cls      = Microwatt,
+            device       = "LFE5UM",
             **kwargs)
 
         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
@@ -39,28 +42,59 @@ class TestSoC(BaseSoC):
         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
 
-# Build --------------------------------------------------------------------------------------------
+class ULX3S85FTestSoC(ulx3s.BaseSoC):
+    def __init__(self, sys_clk_freq=int(16e6), **kwargs):
+        kwargs["integrated_rom_size"] = 0x10000
+        #kwargs["integrated_main_ram_size"] = 0x1000
+        kwargs["csr_data_width"] = 32
+        kwargs["l2_size"] = 0
+        #bus_data_width = 16,
+
+        ulx3s.BaseSoC.__init__(self,
+            sys_clk_freq = sys_clk_freq,
+            cpu_type     = "external",
+            cpu_cls      = LibreSoC,
+            cpu_variant  = "standardjtag",
+            #cpu_cls      = Microwatt,
+            device       = "LFE5U-85F",
+            **kwargs)
+
+# Build
+# ----------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(
-                      description="LiteX SoC with LibreSoC CPU on Versa ECP5")
+    parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
+                                     "CPU on Versa ECP5 or ULX3S LFE5U85F")
     parser.add_argument("--build", action="store_true", help="Build bitstream")
-    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--load", action="store_true", help="Load bitstream")
     parser.add_argument("--sys-clk-freq",  default=int(16e6),
-                         help="System clock frequency (default=16MHz)")
+                        help="System clock frequency (default=16MHz)")
+    parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
+                        "to build for/load to")
 
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
-                  **soc_sdram_argdict(args))
+    if args.fpga == "versa_ecp5":
+        soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+                               **soc_sdram_argdict(args))
+
+    elif args.fpga == "ulx3s85f":
+        soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+                              **soc_sdram_argdict(args))
+
+    else:
+        soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+                               **soc_sdram_argdict(args))
+
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
     if args.load:
         prog = soc.platform.create_programmer()
-        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
+        prog.load_bitstream(os.path.join(builder.gateware_dir,
+                                         soc.build_name + ".svf"))
 
 if __name__ == "__main__":
     main()