return d_out.valid instead of always "ok" in MMU FSM

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index aeffb5c2005e7cf1cca26cff6ed7b895b4fe3e64..abcc06cf8963060808025afebd904d8bab1055ba 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -76,8 +76,8 @@ class LoadStore1(PortInterfaceBase):
 
     def set_wr_data(self, m, data, wen):
         m.d.sync += self.d_in.data.eq(data) # one cycle **AFTER** valid raised
-        # TODO set wen
-        st_ok = Const(1, 1)
+        #m.d.sync += self.d_in.byte_sel.eq(wen) # ditto
+        st_ok = self.d_out.valid # indicates write data is valid
         return st_ok
 
     def get_rd_data(self, m):