create and use ShiftRotPipeSpec

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index eed4dffe4d37787863c57213154df910a33914f6..3937052201ca1f684e6b458352100acf36fb8e71 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -2,7 +2,8 @@ from nmigen import Signal, Const
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.alu.pipe_data import ALUOutputData, IntegerData
+from nmutil.dynamicpipe import SimpleHandshakeRedir
 
 
 class ShiftRotInputData(IntegerData):
@@ -33,3 +34,15 @@ class ShiftRotInputData(IntegerData):
                       self.rb.eq(i.rb),
                       self.xer_ca.eq(i.xer_ca),
                       self.xer_so.eq(i.xer_so)]
+
+
+# TODO: replace CompALUOpSubset with CompShiftRotOpSubset
+class ShiftRotPipeSpec:
+    regspec = (ShiftRotInputData.regspec, ALUOutputData.regspec)
+    opsubsetkls = CompALUOpSubset
+    def __init__(self, id_wid, op_wid):
+        self.id_wid = id_wid
+        self.op_wid = op_wid
+        self.opkls = lambda _: self.opsubsetkls(name="op")
+        self.stage = None
+        self.pipekls = SimpleHandshakeRedir

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index f8c2880bad908e5fe609cd17a45f43f376b33d51..595d5a3bafc8418da26725f76d8ee03219f37717 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -14,7 +14,7 @@ from soc.decoder.isa.all import ISA
 
 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
 from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
 import random
 
 class TestCase:
@@ -181,9 +181,9 @@ class ShiftRotTestCase(FHDLTestCase):
             self.run_tst_program(Program(lst), initial_regs)
 
     def test_ilang(self):
-        rec = CompALUOpSubset()
+        rec = ShiftRotPipeSpec.opsubsetkls()
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+        pspec = ShiftRotPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = ShiftRotBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
         with open("pipeline.il", "w") as f:
@@ -204,9 +204,9 @@ class TestRunner(FHDLTestCase):
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 
-        rec = CompALUOpSubset()
+        rec = ShiftRotPipeSpec.opsubsetkls()
 
-        pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+        pspec = ShiftRotPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         m.submodules.alu = alu = ShiftRotBasePipe(pspec)
 
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)