We need these outputs to hold stable, so the Issue FSM can know whether
it can return to the Simple-V loop, or must return to Fetch. A good place
to reset these is at the start, before any instruction is executed.
with m.If(exec_insn_valid_i):
comb += core_ivalid_i.eq(1) # instruction is valid
comb += core_issue_i.eq(1) # and issued
with m.If(exec_insn_valid_i):
comb += core_ivalid_i.eq(1) # instruction is valid
comb += core_issue_i.eq(1) # and issued
+ sync += sv_changed.eq(0)
+ sync += pc_changed.eq(0)
m.next = "INSN_ACTIVE" # move to "wait completion"
# instruction started: must wait till it finishes
m.next = "INSN_ACTIVE" # move to "wait completion"
# instruction started: must wait till it finishes
sync += core.e.eq(0)
sync += core.raw_insn_i.eq(0)
sync += core.bigendian_i.eq(0)
sync += core.e.eq(0)
sync += core.raw_insn_i.eq(0)
sync += core.bigendian_i.eq(0)
- sync += sv_changed.eq(0)
- sync += pc_changed.eq(0)
comb += exec_pc_valid_o.eq(1)
with m.If(exec_pc_ready_i):
m.next = "INSN_START" # back to fetch
comb += exec_pc_valid_o.eq(1)
with m.If(exec_pc_ready_i):
m.next = "INSN_START" # back to fetch