update test_issuer_mmu_data_path.py to handle SPRs

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index f6208229a4ea89bd909440c6881f0c4c748aaec2..9d1836e51ae3bf5cc399e5237fb599d4dc296559 100644 (file)
--- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@ -17,12 +17,11 @@ class MMUTestCase(TestAccumulatorBase):
         lst = [
                 "dcbz 1,2",
                 "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
         lst = [
                 "dcbz 1,2",
                 "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R

-                #"mfspr 1, 18",     # DSISR to reg 1
-                #"mfspr 2, 19",     # DAR to reg 2
-                #"mtspr 18, 1",     # TODO
-                #"mtspr 19, 2",     # TODO
-                #"std 1, 0(2)"
-                "lhz 3, 0(1)"       # load some data
+                "mtspr 18, 1",     # reg 1 to DSISR
+                "mtspr 19, 2",     # reg 2 to DAR
+                "mfspr 1, 18",     # DSISR to reg 1
+                "mfspr 2, 19",     # DAR to reg 2
+                "lhz 3, 0(1)"      # load some data

               ]
 
         initial_regs = [0] * 32
               ]
 
         initial_regs = [0] * 32