self.debug_wb_cyc = Signal()
self.debug_wb_stb = Signal()
self.debug_wb_we = Signal()
self.debug_wb_cyc = Signal()
self.debug_wb_stb = Signal()
self.debug_wb_we = Signal()
# subset SPR: first check a few bits
with m.If(~spr[9] & ~spr[5]):
comb += self.debug0.eq(3)
# subset SPR: first check a few bits
with m.If(~spr[9] & ~spr[5]):
comb += self.debug0.eq(3)
comb += l_in.sprn.eq(spr) # which SPR
comb += l_in.rs.eq(a_i) # incoming operand (RS)
comb += done.eq(1) # FIXME l_out.done
comb += l_in.sprn.eq(spr) # which SPR
comb += l_in.rs.eq(a_i) # incoming operand (RS)
comb += done.eq(1) # FIXME l_out.done
# subset SPR: first check a few bits
with m.If(~spr[9] & ~spr[5]):
comb += self.debug0.eq(5)
# subset SPR: first check a few bits
with m.If(~spr[9] & ~spr[5]):
comb += self.debug0.eq(5)
comb += o.data.eq(l_out.sprval) # SPR from MMU
comb += o.ok.eq(l_out.done) # only when l_out valid
comb += done.eq(1) # FIXME l_out.done
comb += o.data.eq(l_out.sprval) # SPR from MMU
comb += o.ok.eq(l_out.done) # only when l_out valid
comb += done.eq(1) # FIXME l_out.done