reduce sdram pins to smaller address and only 1 cs_n

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index a98c639b26b266d1eb0ab3b0ccc76e39d1486a64..8aa713e570b965b36f3cd479fea8e27a198b1ff3 100644 (file)
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -83,7 +83,7 @@ _io = [
     ("sdram", 0,
         Subsignal("a",     Pins(
             "M20 M19 L20 L19 K20 K19 K18 J20",
-            "J19 H20 N19 G20 G19 E14 E15 E16")),
+            "J19 H20 N19 G20 G19")),
         Subsignal("dq_i",    Pins(
             "J16 L18 M18 N18 P18 T18 T17 U20",
             "E19 D20 D19 C20 E18 F18 J18 J17")),
@@ -96,8 +96,8 @@ _io = [
         Subsignal("we_n",  Pins("T20")),
         Subsignal("ras_n", Pins("R20")),
         Subsignal("cas_n", Pins("T19")),
-        Subsignal("cs_n",  Pins("P20 P30")),
-        Subsignal("cke",   Pins("F20 F21")),
+        Subsignal("cs_n",  Pins("P30")),
+        Subsignal("cke",   Pins("F21")),
         Subsignal("ba",    Pins("P19 N20")),
         Subsignal("dm",    Pins("U19 E20")),
         IOStandard("LVCMOS33"),