Convert CR out to enum in power_decoder

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index ad405da6da39988fbaabfdd646f892e1cabacb9e..7a074f5a35901f16399971af9196ef6964694d4b 100644 (file)
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -124,6 +124,7 @@ class PowerOp:
         self.in3_sel = Signal(In3Sel, reset_less=True)
         self.out_sel = Signal(OutSel, reset_less=True)
         self.cr_in = Signal(CRInSel, reset_less=True)
+        self.cr_out = Signal(CROutSel, reset_less=True)
         self.ldst_len = Signal(LdstLen, reset_less=True)
         self.rc_sel = Signal(RC, reset_less=True)
         self.cry_in = Signal(CryIn, reset_less=True)
@@ -148,6 +149,7 @@ class PowerOp:
                self.in3_sel.eq(In3Sel[row['in3']]),
                self.out_sel.eq(OutSel[row['out']]),
                self.cr_in.eq(CRInSel[row['CR in']]),
+               self.cr_out.eq(CROutSel[row['CR out']]),
                self.ldst_len.eq(LdstLen[row['ldst len']]),
                self.rc_sel.eq(RC[row['rc']]),
                self.cry_in.eq(CryIn[row['cry in']]),
@@ -166,6 +168,7 @@ class PowerOp:
                self.in3_sel.eq(otherop.in3_sel),
                self.out_sel.eq(otherop.out_sel),
                self.cr_in.eq(otherop.cr_in),
+               self.cr_out.eq(otherop.cr_out),
                self.rc_sel.eq(otherop.rc_sel),
                self.ldst_len.eq(otherop.ldst_len),
                self.cry_in.eq(otherop.cry_in)]
@@ -181,6 +184,7 @@ class PowerOp:
                    self.in3_sel,
                    self.out_sel,
                    self.cr_in,
+                   self.cr_out,
                    self.ldst_len,
                    self.rc_sel,
                    self.internal_op,

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index bd9b6748822cf06d762e56bf7015f9a60ddd9b4a..1895bce8d1cc5acf3c0e00118d5e2ef3fc744fa7 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -23,7 +23,7 @@ def get_csv(name):
 
 
 # names of the fields in the tables that don't correspond to an enum
-single_bit_flags = ['CR out', 'inv A', 'inv out',
+single_bit_flags = ['inv A', 'inv out',
                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
                     'sgn', 'lk', 'sgl pipe']
 

diff --git a/src/soc/decoder/test/test_power_decoder.py b/src/soc/decoder/test/test_power_decoder.py
index c72ded066cdfc70f027bbe28821084484e8dfe76..6f3798360822b11c2407126231a7f82e79d4b82e 100644 (file)
--- a/src/soc/decoder/test/test_power_decoder.py
+++ b/src/soc/decoder/test/test_power_decoder.py
@@ -26,6 +26,7 @@ class DecoderTestCase(FHDLTestCase):
         in3_sel = Signal(In3Sel)
         out_sel = Signal(OutSel)
         cr_in = Signal(CRInSel)
+        cr_out = Signal(CROutSel)
         rc_sel = Signal(RC)
         ldst_len = Signal(LdstLen)
         cry_in = Signal(CryIn)
@@ -42,6 +43,7 @@ class DecoderTestCase(FHDLTestCase):
                  in3_sel.eq(dut.op.in3_sel),
                  out_sel.eq(dut.op.out_sel),
                  cr_in.eq(dut.op.cr_in),
+                 cr_out.eq(dut.op.cr_out),
                  rc_sel.eq(dut.op.rc_sel),
                  ldst_len.eq(dut.op.ldst_len),
                  cry_in.eq(dut.op.cry_in),
@@ -80,6 +82,7 @@ class DecoderTestCase(FHDLTestCase):
                            (in3_sel, In3Sel, 'in3'),
                            (out_sel, OutSel, 'out'),
                            (cr_in, CRInSel, 'CR in'),
+                           (cr_out, CROutSel, 'CR out'),
                            (rc_sel, RC, 'rc'),
                            (cry_in, CryIn, 'cry in'),
                            (ldst_len, LdstLen, 'ldst len')]