corrections to Makefile for building / not-building 4k sram ls180

diff --git a/Makefile b/Makefile
index b7d73ee58c280d298136d9773db7bffa972747c9..abb446dd00b02008e36f3412235f37be5194d312 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -49,8 +49,8 @@ ls180_4k_verilog:
                        src/soc/litex/florent/libresoc/libresoc.v
 
 # build the litex libresoc SoC without 4k SRAMs
-ls180_4ksram_verilog_build: ls180_verilog
-       make -C soc/soc/litex/florent ls1804k
+ls180_verilog_build: ls180_verilog
+       make -C soc/soc/litex/florent ls180
 
 # build the litex libresoc SoC with 4k SRAMs
 ls180_4ksram_verilog_build: ls180_4k_verilog

diff --git a/libreriscv b/libreriscv
index 365cec3d5377e618199acfdf7f26545238aacdca..3b584fe6ab11bf1d499d28f8cab40d2454bd9585 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 365cec3d5377e618199acfdf7f26545238aacdca
+Subproject commit 3b584fe6ab11bf1d499d28f8cab40d2454bd9585

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index 3f163ae167c3d17b3e8cc2a050a60ab20a6bdba2..47083f3531935d83fd1dfe98faf465cad8804cff 160000 (submodule)
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit 3f163ae167c3d17b3e8cc2a050a60ab20a6bdba2
+Subproject commit 47083f3531935d83fd1dfe98faf465cad8804cff