reduce icache/dcache TLB sizes

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 82b983bd3fd0166235395a3a33d011049e4ab801..910149e50a5dcc73955592d37dc97f8ec4a58690 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -749,9 +749,9 @@ class DCache(Elaboratable, DCacheConfig):
                                  (pspec.microwatt_compat == True))
 
         XLEN = pspec.XLEN
-        TLB_SET_SIZE = 16
+        TLB_SET_SIZE = 8
         TLB_NUM_WAYS = 2
-        NUM_LINES = 16
+        NUM_LINES = 8
         NUM_WAYS = 2
 
         if self.small_cache:

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index ff45332d8fd9a5460464468fcefbffd9e808306f..4e40ce403e94f1536b38e269867496619676293c 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -344,8 +344,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
 
         XLEN = pspec.XLEN
         LINE_SIZE = 64
-        TLB_SIZE = 16
-        NUM_LINES = 16
+        TLB_SIZE = 8
+        NUM_LINES = 8
         NUM_WAYS = 2
         if self.small_cache:
             # reduce way sizes and num lines to ridiculously small