worked out how to dynamically enable carry-in to ALU: test input_carry against CryIn...

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 29f8e4b99b552efaa2f2ef09245fa4b08c464311..1bc486da2cc7014011dc6abaeb84876ecb6b25bd 100644 (file)
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -6,6 +6,7 @@ see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
 """
 from nmigen import Const
 from soc.regfile.regfiles import XERRegs, FastRegs
+from soc.decoder.power_enums import CryIn
 
 
 def regspec_decode(e, regfile, name):
@@ -71,13 +72,10 @@ def regspec_decode(e, regfile, name):
         OV = 1<<XERRegs.OV
         if name == 'xer_so':
             return e.oe.oe[0] & e.oe.oe_ok, SO, SO
-            return Const(1), SO, SO # TODO
         if name == 'xer_ov':
             return e.oe.oe[0] & e.oe.oe_ok, OV, OV
-            return Const(1), OV, OV # TODO
         if name == 'xer_ca':
-            return Const(1), CA, CA # TODO
-            #return e.input_carry, CA, CA
+            return (e.input_carry == CryIn.CA.value), CA, CA
 
     if regfile == 'FAST':
         # FAST register numbering is *unary* encoded

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index ff2adcc5626b6d45b0b45cffa307b48040284e07..a28b92bdc9535d0a243b370e3224b1a3c0f1e379 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -8,6 +8,8 @@ from soc.fu.alu.test.test_pipe_caller import test_data # imports the data
 from soc.fu.compunits.compunits import ALUFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
 
+from soc.decoder.power_enums import CryIn
+
 
 class ALUTestRunner(TestRunner):
     def __init__(self, test_data):
@@ -33,7 +35,7 @@ class ALUTestRunner(TestRunner):
 
         # XER.ca
         cry_in = yield dec2.e.input_carry
-        if True: #cry_in:
+        if cry_in == CryIn.CA.value:
             carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
             carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
             res['xer_ca'] = carry | (carry32<<1)