add div FSM as default for test_issuer in verilog and ilang gen

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index de70df7e22815edb56cfe72a7add91e76c42a081..9cf44a9924faafd76eb5649b3978e7f656a9785a 100644 (file)
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -72,7 +72,7 @@ from soc.fu.trap.pipeline import TrapBasePipe
 from soc.fu.trap.pipe_data import TrapPipeSpec
 
 from soc.fu.div.pipeline import DivBasePipe
-from soc.fu.div.pipe_data import DivPipeSpecDivPipeCore
+from soc.fu.div.pipe_data import DivPipeSpecFSMDivCore
 
 from soc.fu.mul.pipeline import MulBasePipe
 from soc.fu.mul.pipe_data import MulPipeSpec
@@ -162,7 +162,7 @@ class DivFunctionUnit(FunctionUnitBaseSingle):
     fnunit = Function.DIV
 
     def __init__(self, idx):
-        super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx)
+        super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx)
 
 
 class MulFunctionUnit(FunctionUnitBaseSingle):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 3d168da674490010dd2ead87d30f3f1456f6ab6c..168f389f0d57c4800e99c07f6218683607ac9011 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -260,6 +260,7 @@ class TestIssuer(Elaboratable):
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index d77464b545d20da905f319e1c4f379cd9ec35d5b..90b8308131766e5f651ea321d948ef9992dbcee1 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -11,6 +11,7 @@ from soc.simple.issuer import TestIssuer
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',