spurious imports of FHDLTestCase, should be from nmutil

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index 04278c30ca7fcdf5301a8cead03b4dacf4dafc5f..171af5c1416e127c5376cfa98afb75599f820b90 100644 (file)
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,

diff --git a/src/soc/simulator/test_helloworld_sim.py b/src/soc/simulator/test_helloworld_sim.py
index 2ff1e0069f4608101f9a7bd2b554b75fc0066705..d11304378a1991c51d2168b585fd5de82e34f17b 100644 (file)
--- a/src/soc/simulator/test_helloworld_sim.py
+++ b/src/soc/simulator/test_helloworld_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,

diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index ef117c3a2d127f25087091ac63786002fdc41b42..6d251056aeb34041927ec1f7773935627e894382 100644 (file)
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,

diff --git a/src/soc/simulator/test_shift_sim.py b/src/soc/simulator/test_shift_sim.py
index 3ac85998375c499aa9a615bf69c4712911beee89..e1642105e4cee51f3df366a1bd8c34b89031197c 100644 (file)
--- a/src/soc/simulator/test_shift_sim.py
+++ b/src/soc/simulator/test_shift_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index dae60ceaf0aad1c486e460d29d4f8b9377e7c242..d6343ae51d4f2266750cea1060f16928161066c7 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,

diff --git a/src/soc/simulator/test_trap_sim.py b/src/soc/simulator/test_trap_sim.py
index d535cf1a76695443d27ccd5fc96c256073b9b887..1c79482639aa88c4511984ac217406693dc62b8e 100644 (file)
--- a/src/soc/simulator/test_trap_sim.py
+++ b/src/soc/simulator/test_trap_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,