projects / soc.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (from parent 1: 7592c8b)
add CR1 to power_enums
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Dec 2020 20:30:34 +0000 (20:30 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 28 Dec 2020 20:30:37 +0000 (20:30 +0000)
src/soc/decoder/power_enums.py patch | blob | history

diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index 743203653d942cdfc2068102e31d136d740766ab..b33cb2777492be1601e14b044d95a4f00e281229 100644 (file)
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -294,6 +294,7 @@ class CRInSel(Enum):
     BA_BB = 4
     BC = 5
     WHOLE_REG = 6
+    CR1 = 7
 
 
 @unique
@@ -303,6 +304,7 @@ class CROutSel(Enum):
     BF = 2
     BT = 3
     WHOLE_REG = 4
+    CR1 = 5
 
 
 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and