manually run coresync clock for test issuer

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index 012e5b198a4c5826df5d9d0a00de9776e0f64b8a..f38bbcf60d94f9028f9df4be953c66664173302d 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -4,7 +4,7 @@ related bugs:
 
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
 """
 
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
 """

-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat, ClockSignal

 
 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
 # Also, check out the cxxsim nmigen branch, and latest yosys from git
 
 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
 # Also, check out the cxxsim nmigen branch, and latest yosys from git


@@ -164,6 +164,10 @@ class TestRunner(FHDLTestCase):
         simdec2 = PowerDecode2(simdec)
         m.submodules.simdec2 = simdec2  # pain in the neck
 
         simdec2 = PowerDecode2(simdec)
         m.submodules.simdec2 = simdec2  # pain in the neck
 

+        # run core clock at same rate as test clock
+        intclk = ClockSignal("coresync")
+        comb += intclk.eq(ClockSignal())
+

         comb += issuer.pc_i.data.eq(pc_i)
 
         # nmigen Simulation
         comb += issuer.pc_i.data.eq(pc_i)
 
         # nmigen Simulation