output ilang to branch_pipeline.il for branch

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 898afa8d23f4c8be965de5e72bc8fd3824c3f647..8666a4164d8fcd184b1f902a0266add30bcea5c9 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -104,7 +104,7 @@ class BranchTestCase(FHDLTestCase):
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = BranchBasePipe(pspec)
         vl = rtlil.convert(alu, ports=alu.ports())
-        with open("logical_pipeline.il", "w") as f:
+        with open("branch_pipeline.il", "w") as f:
             f.write(vl)