sigh, issue with detection/waiting for LD/ST CompUnit

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 62ad9ec2ae1699a544f84ecc8599ddada3a61b8a..085f478802222c88ea87018448c2d6979b0fb400 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -82,11 +82,17 @@ def get_cu_outputs(cu, code):
     res = {}
     # wait for pipeline to indicate valid.  this because for long
     # pipelines (or FSMs) the write mask is only valid at that time.
-    while True:
-        valid_o = yield cu.alu.n.valid_o
-        if valid_o:
-            break
-        yield
+    if hasattr(cu, "alu"): # ALU CompUnits
+        while True:
+            valid_o = yield cu.alu.n.valid_o
+            if valid_o:
+                break
+            yield
+    else: # LDST CompUnit
+        # not a lot can be done about this - simply wait a few cycles
+        for i in range(10):
+            yield
+
     wrmask = yield cu.wrmask
     wr_rel_o = yield cu.wr.rel
     print("get_cu_outputs", cu.n_dst, wrmask, wr_rel_o)
@@ -283,6 +289,7 @@ class TestRunner(FHDLTestCase):
             yield cu.rdmaskn.eq(0)
             yield
 
+
             # debugging issue with branch
             if self.funit == Function.BRANCH:
                 lr = yield cu.alu.pipe1.n.data_o.lr.data