too much debug info going past, so add the test registers to the
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 24 Jul 2020 13:42:04 +0000 (14:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 24 Jul 2020 13:42:04 +0000 (14:42 +0100)
failed log message

src/soc/fu/div/test/runner.py

index e822e41cb590b6d7379626c49b23126dfc090a0c..5404c773e94dd4e4f339508b33af8553966b6692 100644 (file)
@@ -190,6 +190,7 @@ class DivRunner(unittest.TestCase):
                         # XXX print("time:", sim._state.timeline.now)
                         msg = "%s: %s" % (self.div_pipe_kind.name, code)
                         msg += " %s" % (repr(prog.assembly))
                         # XXX print("time:", sim._state.timeline.now)
                         msg = "%s: %s" % (self.div_pipe_kind.name, code)
                         msg += " %s" % (repr(prog.assembly))
+                        msg += " %s" % (repr(test.regs))
                         yield from self.check_alu_outputs(alu, pdecode2,
                                                           isa_sim, msg)
 
                         yield from self.check_alu_outputs(alu, pdecode2,
                                                           isa_sim, msg)