mention zeroing

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 4749f4a3fc46a520a11edfbd6238369fd092f614..048e5b4ca9632b5bf8d4ca10b4a79a38bc497f22 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -259,6 +259,8 @@ class LDSTCompUnit(Elaboratable):
         alu_o = Signal(self.rwid, reset_less=True)
         ldd_o = Signal(self.rwid, reset_less=True)
 
+        # XXX TODO ZEROing just lije in ComUnit
+
         # select immediate or src2 reg to add
         src2_or_imm = Signal(self.rwid, reset_less=True)
         src_sel = Signal(reset_less=True)