reorder / reorganise reset signals slightly

diff --git a/src/soc/clock/select.py b/src/soc/clock/select.py
index 23286b7a79906b4f0281eb2a8ebd6fb6931188dc..5ca7ba9065fcc4f7e038e2c74375f7cc7e4fa6b3 100644 (file)
--- a/src/soc/clock/select.py
+++ b/src/soc/clock/select.py
@@ -35,12 +35,10 @@ class ClockSelect(Elaboratable):
         self.pll_48_o = Signal()  # 6-divide (test signal) from PLL
         self.clk_sel_i = Signal(3) # clock source selection
         self.core_clk_o = Signal() # main core clock (selectable)
         self.pll_48_o = Signal()  # 6-divide (test signal) from PLL
         self.clk_sel_i = Signal(3) # clock source selection
         self.core_clk_o = Signal() # main core clock (selectable)

-        self.rst        = Signal() # reset

 
     def elaborate(self, platform):
         m = Module()
         comb, sync = m.d.comb, m.d.sync
 
     def elaborate(self, platform):
         m = Module()
         comb, sync = m.d.comb, m.d.sync

-        m.d.comb += ResetSignal().eq(self.rst)

 
         # array of clocks (selectable by clk_sel_i)
         clkgen = Array([Signal(name="clk%d" % i) for i in range(8)])
 
         # array of clocks (selectable by clk_sel_i)
         clkgen = Array([Signal(name="clk%d" % i) for i in range(8)])


@@ -79,12 +77,10 @@ class DummyPLL(Elaboratable):
     def __init__(self):
         self.clk_24_i = Signal() # 24 mhz external incoming
         self.clk_pll_o = Signal()  # output fake PLL clock
     def __init__(self):
         self.clk_24_i = Signal() # 24 mhz external incoming
         self.clk_pll_o = Signal()  # output fake PLL clock

-        self.rst = Signal() # reset

 
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
 
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through

-        m.d.comb += ResetSignal().eq(self.rst)

 
         return m
 
 
         return m
 

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 7479be12c02e3adc15227df3badb4e86520be2c7..a788fb5a132c7cd518dbdfb06214b6f33f2e6110 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -100,7 +100,6 @@ class NonProductionCore(Elaboratable):
 
         # start/stop and terminated signalling
         self.core_stopped_i = Signal(reset_less=True)
 
         # start/stop and terminated signalling
         self.core_stopped_i = Signal(reset_less=True)

-        self.core_reset_i = Signal()

         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 
         # create per-FU instruction decoders (subsetted)
         self.core_terminate_o = Signal(reset=0)  # indicates stopped
 
         # create per-FU instruction decoders (subsetted)


@@ -146,9 +145,6 @@ class NonProductionCore(Elaboratable):
         self.connect_rdports(m, fu_bitdict)
         self.connect_wrports(m, fu_bitdict)
 
         self.connect_rdports(m, fu_bitdict)
         self.connect_wrports(m, fu_bitdict)
 

-        # connect up reset
-        m.d.comb += ResetSignal().eq(self.core_reset_i)
-

         return m
 
     def connect_instruction(self, m):
         return m
 
     def connect_instruction(self, m):

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 06911b6348d1b9dae09e01ad060b462828414b9e..8302ff5065e08d912541f1002f91d4cd9e89378d 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -157,13 +157,17 @@ class TestIssuerInternal(Elaboratable):
         core_sync = ClockDomain("coresync")
         m.domains += cd_por, cd_sync, core_sync
 
         core_sync = ClockDomain("coresync")
         m.domains += cd_por, cd_sync, core_sync
 

+        ti_rst = Signal(reset_less=True)

         delay = Signal(range(4), reset=3)
         with m.If(delay != 0):
             m.d.por += delay.eq(delay - 1)
         comb += cd_por.clk.eq(ClockSignal())
         comb += core_sync.clk.eq(ClockSignal())
         delay = Signal(range(4), reset=3)
         with m.If(delay != 0):
             m.d.por += delay.eq(delay - 1)
         comb += cd_por.clk.eq(ClockSignal())
         comb += core_sync.clk.eq(ClockSignal())

+

         # power-on reset delay 
         # power-on reset delay 

-        comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
+        core_rst = ResetSignal("coresync")
+        comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
+        comb += core_rst.eq(ti_rst)

 
         # busy/halted signals from core
         comb += self.busy_o.eq(core.busy_o)
 
         # busy/halted signals from core
         comb += self.busy_o.eq(core.busy_o)


@@ -235,7 +239,7 @@ class TestIssuerInternal(Elaboratable):
                 sync += core.e.eq(0)
                 sync += core.raw_insn_i.eq(0)
                 sync += core.bigendian_i.eq(0)
                 sync += core.e.eq(0)
                 sync += core.raw_insn_i.eq(0)
                 sync += core.bigendian_i.eq(0)

-                with m.If(~dbg.core_stop_o & ~core.core_reset_i):
+                with m.If(~dbg.core_stop_o & ~core_rst):

                     # instruction allowed to go: start by reading the PC
                     # capture the PC and also drop it into Insn Memory
                     # we have joined a pair of combinatorial memory
                     # instruction allowed to go: start by reading the PC
                     # capture the PC and also drop it into Insn Memory
                     # we have joined a pair of combinatorial memory


@@ -475,8 +479,10 @@ class TestIssuer(Elaboratable):
         comb += pll.clk_24_i.eq(clksel.clk_24_i)
 
         # now wire up ResetSignals.  don't mind them all being in this domain
         comb += pll.clk_24_i.eq(clksel.clk_24_i)
 
         # now wire up ResetSignals.  don't mind them all being in this domain

-        comb += pll.rst.eq(ResetSignal())
-        comb += clksel.rst.eq(ResetSignal())
+        int_rst = ResetSignal("intclk")
+        pll_rst = ResetSignal("pllclk")
+        comb += int_rst.eq(ResetSignal())
+        comb += pll_rst.eq(ResetSignal())

 
         return m
 
 
         return m
 


@@ -487,8 +493,8 @@ class TestIssuer(Elaboratable):
 
     def external_ports(self):
         ports = self.ti.external_ports()
 
     def external_ports(self):
         ports = self.ti.external_ports()

-        #ports.append(ClockSignal())
-        #ports.append(ResetSignal())
+        ports.append(ClockSignal())
+        ports.append(ResetSignal())

         ports.append(self.clksel.clk_sel_i)
         ports.append(self.clksel.pll_48_o)
         return ports
         ports.append(self.clksel.clk_sel_i)
         ports.append(self.clksel.pll_48_o)
         return ports