shrink JTAG master bus to 32-bit (match with litex)

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
index c2a6f0958a86ce1f94ec6a539e9ca08f3b16b8ba..52d236f4159d1fa9683f8b939cdee9406d02e60c 100644 (file)
--- a/src/soc/debug/jtag.py
+++ b/src/soc/debug/jtag.py
@@ -62,7 +62,8 @@ class Pins:
 
 
 class JTAG(DMITAP, Pins):
-    def __init__(self, pinset, wb_data_wid=64):
+    # 32-bit data width here so that it matches with litex
+    def __init__(self, pinset, wb_data_wid=32):
         DMITAP.__init__(self, ir_width=4)
         Pins.__init__(self, pinset)
 
@@ -80,8 +81,9 @@ class JTAG(DMITAP, Pins):
         self.sr = self.add_shiftreg(ircode=4, length=3)
 
         # create and connect wishbone
-        self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
-                                   address_width=29, data_width=wb_data_wid,
+        self.wb = self.add_wishbone(ircodes=[5, 6, 7],
+                                   features={'err', 'stall'},
+                                   address_width=30, data_width=wb_data_wid,
                                    granularity=8, # 8-bit wide
                                    name="jtag_wb")
 
@@ -110,6 +112,10 @@ class JTAG(DMITAP, Pins):
         with m.If(self.sr_en.ie):
             m.d.comb += self.sr_en.i.eq(en_sigs)
 
+        # create a fake "stall"
+        wb = self.wb
+        m.d.comb += wb.stall.eq(wb.cyc & ~wb.ack) # No burst support
+
         return m
 
     def external_ports(self):