add in more CR debug statements

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 34ae0eae8de11bda5222a4dfa48cc2bf6ec2dfad..ec738383cb8e47bcf4c02ea844769a70e5dbc26b 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -241,12 +241,14 @@ class TestRunner(FHDLTestCase):
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
+        print ("check extra output", repr(code), cridx_ok, cridx)
         if rc:
             self.assertEqual(cridx, 0, code)
 
         if cridx_ok:
             cr_expected = sim.crl[cridx].get_range().value
             cr_actual = yield alu.n.data_o.cr0.data
+            print ("CR", cridx, cr_expected, cr_actual)
             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
 
         cry_out = yield dec2.e.output_carry

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 049a276ed4819fac7a15864b74e8200ee07dc0c4..b5d55a4bebb9921327ad87429dff9a477c0bdab5 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -229,6 +229,8 @@ class TestRunner(FHDLTestCase):
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
+        print ("check extra output", repr(code), cridx_ok, cridx)
+
         if rc:
             self.assertEqual(cridx_ok, 1, code)
             self.assertEqual(cridx, 0, code)
@@ -236,6 +238,7 @@ class TestRunner(FHDLTestCase):
         if cridx_ok:
             cr_expected = sim.crl[cridx].get_range().value
             cr_actual = yield from get_cu_output(cu, 1, code)
+            print ("CR", cridx, cr_expected, cr_actual)
             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
 
         cry_out = yield dec2.e.output_carry