loadstore1 now reports exception reason

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index c0f880b4408df8e569e87b2b8c7eb823a5681b45..cf34705920a750c2f0c095f61a42f81fb0938dab 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -131,9 +131,11 @@ def _test_loadstore1(dut, mem):
     print("=== alignment error ===")
     addr = 0xFF100e0FF
     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=1)
-    yield #wait one cycle
+    alignment = yield pi.exc_o.alignment
+    happened = yield pi.exc_o.happened
     dar = yield pi.dar_o
-    #assert(reason==alignment)
+    assert(happened==1)
+    assert(alignment==1)
     assert(dar==addr)
     print("=== alignment error test passed ===")
 

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index e013f3c5163fd0ff5011232a4ecaad0ec9a35960..e7ecf272ffd99848e8e6ce8f39026688992d6505 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -190,7 +190,6 @@ class LoadStore1(PortInterfaceBase):
         # a request when MMU_LOOKUP completes.
         m.d.comb += self.d_validblip.eq(rising_edge(m, self.d_valid))
         ldst_r = LDSTRequest("ldst_r")
-        
         comb += Display("MMUTEST: LoadStore1 d_in.error=%i",d_in.error)
 
         # fsm skeleton
@@ -257,7 +256,7 @@ class LoadStore1(PortInterfaceBase):
                         # instruction lookup fault: store address in DAR
                         comb += exc.happened.eq(1) # reason = MMU_LOOKUP
                         # mark dar as updated ?
-                        sync += self.pi.dar_o.eq(self.addr)
+                        comb += self.pi.dar_o.eq(self.addr)
 
                 with m.If(m_in.err):
                     # MMU RADIX exception thrown
@@ -276,8 +275,7 @@ class LoadStore1(PortInterfaceBase):
         with m.If(self.align_intr):
             comb += exc.happened.eq(1) # reason = alignment
             sync += Display("alignment error: store addr in DAR %x", self.addr)
-            sync += self.pi.dar_o.eq(self.addr)
-            # TODO report reason
+            comb += self.pi.dar_o.eq(self.addr)
 
         # happened, alignment, instr_fault, invalid.
         # note that all of these flow through - eventually to the TRAP