unit test: pass bool mmu

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 691d9a71357b2fd2211e946fa0f4d731f2b70775..6863fff3d61f1bc0234f1be3cbbba35e78fc60e8 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -16,7 +16,7 @@ class Register:
     def __init__(self, num):
         self.num = num
 
-def run_tst(generator, initial_regs, initial_sprs=None, svstate=0):
+def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False):
     if initial_sprs is None:
         initial_sprs = {}
     m = Module()
@@ -34,7 +34,8 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0):
                     initial_insns=gen, respect_pc=True,
                     initial_svstate=svstate,
                     disassembly=insncode,
-                    bigendian=0)
+                    bigendian=0,
+                    mmu=mmu)
     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
     sim = Simulator(m)
 

diff --git a/src/soc/decoder/isa/test_caller_radix.py b/src/soc/decoder/isa/test_caller_radix.py
index 9b92cf811da0047a1070b7479ad5865049b2ec5b..a892e4c1631995200905186d127ce196867ea211 100644 (file)
--- a/src/soc/decoder/isa/test_caller_radix.py
+++ b/src/soc/decoder/isa/test_caller_radix.py
@@ -26,7 +26,7 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
-        simulator = run_tst(prog, initial_regs)
+        simulator = run_tst(prog, initial_regs,mmu=True)
         simulator.gpr.dump()
         return simulator