add XICS memory regions, shrink litex CSR memmap size to do it

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 136d31d45dfdfdef6df3ca7585bcd806f7cf9649..cf072784faf5e85c64c0723d0bc9ba7c3fd03f16 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -61,7 +61,7 @@ class LibreSoC(CPU):
             self.data_width           = 64
         self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
 
-        self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=3)
+        self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=5)
         self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=14)
 
         self.ics_buses = [icp, ics]

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 01c11740e80ed43ca3917b820344b7ad1d773874..69a497b471f5898f4e49a08700e5a815315990bb 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -25,6 +25,10 @@ from litex.tools.litex_sim import Platform
 from libresoc import LibreSoC
 from microwatt import Microwatt
 
+# HACK!
+from litex.soc.integration.soc import SoCCSRHandler
+SoCCSRHandler.supported_address_width.append(12)
+
 # LibreSoCSim -----------------------------------------------------------------
 
 class LibreSoCSim(SoCSDRAM):
@@ -54,9 +58,18 @@ class LibreSoCSim(SoCSDRAM):
         #ram_fname = None
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "micropython/firmware.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/xics/xics.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
                     "hello_world/hello_world.bin"
 
+        # reserve XICS ICP and XICS memory addresses.
+        # TODO: not have these conflict with csr locations
+        self.mem_map['icp'] = 0xc0004000
+        self.mem_map['ics'] = 0xc0005000
+        #self.csr_map["icp"] = 8  #  8 x 0x800 == 0x4000
+        #self.csr_map["ics"] = 10 # 10 x 0x800 == 0x5000
+
         ram_init = []
         if ram_fname:
             #ram_init = get_mem_data({
@@ -80,6 +93,7 @@ class LibreSoCSim(SoCSDRAM):
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
             #bus_data_width           = 64,
+            csr_address_width        = 12, # limit to 0x4000
             cpu_variant              = variant,
             csr_data_width            = 32,
             l2_size             = 0,
@@ -95,6 +109,17 @@ class LibreSoCSim(SoCSDRAM):
             )
         self.platform.name = "sim"
 
+        # XICS interrupt devices
+        icp_addr = self.mem_map['icp']
+        icp_wb = self.cpu.xics_icp
+        icp_region = SoCRegion(origin=icp_addr, size=0x1000, cached=False)
+        self.bus.add_slave(name='icp', slave=icp_wb, region=icp_region)
+
+        ics_addr = self.mem_map['ics']
+        ics_wb = self.cpu.xics_ics
+        ics_region = SoCRegion(origin=ics_addr, size=0x20, cached=False)
+        self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region)
+
         # CRG -----------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))