add build commands to Makefile for versa ecp5
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 10 Nov 2020 19:44:09 +0000 (19:44 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 10 Nov 2020 19:44:09 +0000 (19:44 +0000)
Makefile
src/soc/litex/florent/Makefile

index 9d7ae554eb38300625e81f7360b4a75107120e2f..cd8c001dce74d25484ef460619d40e756170f96b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -18,14 +18,16 @@ develop:
        python3 src/soc/decoder/pseudo/pywriter.py
 
 run_sim: install
-       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/\
-       libresoc/libresoc.v
+       python3 src/soc/simple/issuer_verilog.py \
+                       src/soc/litex/florent/libresoc/libresoc.v
        python3 src/soc/litex/florent/sim.py --cpu=libresoc
 
 testgpio_run_sim:
-       python3 src/soc/simple/issuer_verilog.py src/soc/litex/florent/libresoc/\
-       libresoc.v --enable-testgpio
-       python3 src/soc/litex/florent/sim.py --cpu=libresoc --variant=standardjtagtestgpio
+       python3 src/soc/simple/issuer_verilog.py \
+                       src/soc/litex/florent/libresoc/libresoc.v \
+                       --enable-testgpio
+       python3 src/soc/litex/florent/sim.py --cpu=libresoc \
+                       --variant=standardjtagtestgpio
 
 test: install
        python3 setup.py test # could just run nosetest3...
index 4c88950097a729a823269c40ebe753097344d3b4..754d5d083956ec4b9df405784b30d0c6ee511972 100644 (file)
@@ -10,3 +10,9 @@ ls180:
        yosys -p 'read_ilang ls180_cvt.il' \
           -p 'read_ilang libresoc_cvt.il' \
           -p 'write_ilang ls180.il'
+
+versaecp5:
+        ./versa_ecp5.py --sys-clk-freq=55e6 --build
+
+versaecp5load:
+       ./versa_ecp5.py --sys-clk-freq=55e6 --load