projects / soc.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (from parent 1: 5dc6b70)
swap jtag pinorder to match ulx3s
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 3 Nov 2020 13:53:41 +0000 (13:53 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 3 Nov 2020 13:53:41 +0000 (13:53 +0000)
src/soc/litex/florent/versa_ecp5.py patch | blob | history

diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index 75e33bc25a80e6fe827bc22629b6d31b63b1659a..464e94125c1b6ffa8a0c193bcba2d5e49b4fc072 100755 (executable)
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -43,9 +43,9 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
         # define the pins, add as an extension, *then* request it
         jtag_ios = [
             ("jtag", 0,
-                Subsignal("tck", Pins("B19"), IOStandard("LVCMOS25")),
+                Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS25")),
                 Subsignal("tms", Pins("B12"), IOStandard("LVCMOS25")),
-                Subsignal("tdi", Pins("B9"), IOStandard("LVCMOS25")),
+                Subsignal("tck", Pins("B9"), IOStandard("LVCMOS25")),
                 Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS25")),
             )
         ]