from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
from soc.fu.cr.test.test_pipe_caller import CRTestCase
from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
from soc.fu.cr.test.test_pipe_caller import CRTestCase
-#from soc.fu.branch.test.test_pipe_caller import BranchTestCase
-#from soc.fu.spr.test.test_pipe_caller import SPRTestCase
+# from soc.fu.branch.test.test_pipe_caller import BranchTestCase
+# from soc.fu.spr.test.test_pipe_caller import SPRTestCase
from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
# set up bigendian (TODO: don't do this, use MSR)
yield issuer.core_bigendian_i.eq(bigendian)
# set up bigendian (TODO: don't do this, use MSR)
yield issuer.core_bigendian_i.eq(bigendian)
yield from setup_i_memory(imem, pc, instructions)
yield from setup_test_memory(l0, sim)
yield from setup_i_memory(imem, pc, instructions)
yield from setup_test_memory(l0, sim)
- print ("after test %s reg %2d value %x" % \
- (test.name, int_reg, value))
+ print("after test %s reg %2d value %x" %
+ (test.name, int_reg, value))
traces += [
{'comment': 'microwatt_mmu'},
'core.fus.mmu0.alu_mmu0.illegal',
traces += [
{'comment': 'microwatt_mmu'},
'core.fus.mmu0.alu_mmu0.illegal',