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add extra variant to litex core
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 15 Oct 2020 14:59:21 +0000 (15:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 15 Oct 2020 14:59:21 +0000 (15:59 +0100)
src/soc/litex/florent/libresoc/core.py patch | blob | history

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 9703cbfee6127cbe3a78e002aeb3c92542e9f2e3..81bd0dfc400087e6fc09f3fbf1c42d380d93550c 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -13,7 +13,8 @@ from libresoc.ls180 import io
 from litex.build.generic_platform import ConstraintManager
 
 
-CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
+CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180",
+                "standardjtagnoirq"]
 
 
 def make_wb_bus(prefix, obj, simple=False):