whoops TLBIE must *clear* the valid bit not set it. TLBUpdate

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index cc3b2efca3f07f730eb6adfe570a842d67d0d5a0..82b115bbba9f4b275e57c54ec5570f77ef06081c 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -465,7 +465,7 @@ class DTLBUpdate(Elaboratable):
             pass # clear all back in parent
         with m.Elif(self.tlbie):
             with m.If(self.tlb_hit):
-                comb += db_out.bit_select(self.tlb_hit_way, 1).eq(1)
+                comb += db_out.bit_select(self.tlb_hit_way, 1).eq(0)
                 comb += self.v_updated.eq(1)
 
         with m.Elif(self.tlbwe):