whoops test gets copied 4 times on the If.

create intermediate signal

diff --git a/src/soc/fu/alu/output_stage.py b/src/soc/fu/alu/output_stage.py
index 3ea71b56f72e0a69607a1dc463d02d658a56d54e..0080ca54dfdf205f378dd243bb96aec3ed54e7a2 100644 (file)
--- a/src/soc/fu/alu/output_stage.py
+++ b/src/soc/fu/alu/output_stage.py
@@ -28,7 +28,9 @@ class ALUOutputStage(CommonOutputStage):
         # copy overflow and sticky-overflow.  indicate to CompALU if they
         # are actually required (oe enabled/set) otherwise the CompALU
         # can (will) ignore them.
-        with m.If(op.oe.oe & op.oe.oe_ok):
+        oe = Signal(reset_less=True)
+        comb += oe.eq(op.oe.oe & op.oe.oe_ok)
+        with m.If(oe):
             comb += self.o.xer_so.data.eq(self.so)
             comb += self.o.xer_so.ok.eq(1)
             comb += self.o.xer_ov.data.eq(xer_ov_i)