add mtmsr internal op

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 79e40ec5a840f21ed179bb44ac38bb420acd0433..45b60fb9da2fa2a81abee144c9f4f28da86bbd8e 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -44,6 +44,7 @@ def instr_is_priv(m, op, insn):
         with m.Case(InternalOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
         with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
         with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
+        with m.Case(InternalOp.OP_MTMSR): comb += is_priv_insn.eq(1)
         with m.Case(InternalOp.OP_RFID)  : comb += is_priv_insn.eq(1)
         with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
     with m.If(op == OP_MFSPR | op == OP_MTSPR):