fix MMU lookup after 2nd request (misaligned) by also updating the

ldst_r with the next address/byte_sel

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index 13a6909ad711ceca05c0077957f99425299af88f..a21a4e0884c114eb8d454601ad1d4aa79f484869 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -921,7 +921,7 @@ def test_loadstore1_microwatt_mmu_bin_test5():
 
     m, cmpi = setup_mmu()
 
-    mem = pagetables.microwatt_test2
+    mem = pagetables.microwatt_test5
 
     # nmigen Simulation
     sim = Simulator(m)

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index ce77353a74bb792d1cb773d3c301e9bce05c3061..36836c674984cfc8c5ad870ed4a9eefcc9991d1b 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -306,6 +306,8 @@ class LoadStore1(PortInterfaceBase):
                         comb += self.req.raddr.eq(ldst_r.raddr + 8)
                         comb += self.req.byte_sel.eq(ldst_r.byte_sel[8:])
                         comb += self.req.alignstate.eq(Misalign.WAITSECOND)
+                        sync += ldst_r.raddr.eq(ldst_r.raddr + 8)
+                        sync += ldst_r.byte_sel.eq(ldst_r.byte_sel[8:])
                         sync += ldst_r.alignstate.eq(Misalign.WAITSECOND)
                         sync += Display("    second req %x", self.req.raddr)
                     with m.Elif(ldst_r.alignstate == Misalign.WAITSECOND):