comment out invalid test
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 25 May 2020 02:26:46 +0000 (03:26 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 25 May 2020 02:26:46 +0000 (03:26 +0100)
src/soc/experiment/compalu_multi.py

index 876f5f8a03a25a949f1d8d7fc39a22f684730d29..c1a555d16a2b965e7ad54b26c57822a0e9793ee7 100644 (file)
@@ -354,9 +354,11 @@ def scoreboard_sim(dut):
     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
     assert result == 65532
 
-    result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
-                                    imm=8, imm_ok=1)
-    assert result == 8
+    # XXX - immediate and zero is not a POWER mode (and won't work anyway)
+    # reason: no actual operands.
+    #result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
+    #                                imm=8, imm_ok=1)
+    #assert result == 8
 
     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
     assert result == 2