addcomments for MMU PortInterface test (how it, um, doesnt actually use PortInterface? :)

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index 46cc55719ec8b1074598ff9cb205502617dc5737..ea342ba35e9c62d5f999d654bde51cf0d705ead7 100644 (file)
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -1,3 +1,9 @@
+"""MMU PortInterface Test
+
+quite basic, goes directly to the MMU to assert signals (does not
+yet use PortInterface)
+"""
+
 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
 from nmigen.cli import main
 from nmigen.cli import rtlil