correct comments in sv.add rc=1

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 8761fdc4320b911a66dc244c3fadacd78666ad0c..92e8522aecd8b5d3df0df7b630b24ef81a0e7817 100644 (file)
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -76,9 +76,10 @@ class SVP64ALUTestCase(TestAccumulatorBase):
                       initial_svstate=svstate)
 
     def case_4_sv_add_(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
-        #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
+        # adds when Rc=1:                               TODO CRs higher up
+        #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
+        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
+
         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)