- core_sync = ClockDomain("coresync")
- m.domains += cd_por, cd_sync, core_sync
+ m.domains += cd_por, cd_sync
ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
# add 2 clock domains established above...
cd_int = ClockDomain("intclk")
cd_pll = ClockDomain("pllclk")
# add 2 clock domains established above...
cd_int = ClockDomain("intclk")
cd_pll = ClockDomain("pllclk")
m.domains += cd_pll
# internal clock is set to selector clock-out. has the side-effect of
# running TestIssuer at this speed (see DomainRenamer("intclk") above)
m.domains += cd_pll
# internal clock is set to selector clock-out. has the side-effect of
# running TestIssuer at this speed (see DomainRenamer("intclk") above)
# PLL clock established. has the side-effect of running clklsel
# at the PLL's speed (see DomainRenamer("pllclk") above)
# PLL clock established. has the side-effect of running clklsel
# at the PLL's speed (see DomainRenamer("pllclk") above)